Skip to content

[SYCL][DOC] Fix path to FPGA device selector in doc #2563

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Oct 5, 2020
Merged

Conversation

Ruyk
Copy link
Contributor

@Ruyk Ruyk commented Sep 29, 2020

The documentation for the FPGA Selector points now to the uppercase INTEL directory instead of lowercase.

The documentation for the FPGA Selector points now to the uppercase INTEL directory instead of lowercase.
@Ruyk Ruyk requested a review from a team as a code owner September 29, 2020 15:02
@Ruyk
Copy link
Contributor Author

Ruyk commented Oct 5, 2020

@bader / @pvchupin ? Who has the power to review and approve this? :-)

@Fznamznon
Copy link
Contributor

@bader / @pvchupin ? Who has the power to review and approve this? :-)

I think members of dpcpp-specification-reviewers team have it. Team is added to reviewers list. So @intel/dpcpp-specification-reviewers ping.

@bader bader merged commit ca33f7f into intel:sycl Oct 5, 2020
alexbatashev pushed a commit to alexbatashev/llvm that referenced this pull request Oct 7, 2020
* sycl:
  [SYCL] Fix test failure due to size discrepancy in 32 and 64 bit environment (intel#2594)
  [BuildBot] Linux GPU driver uplift to 20.39.17972 (intel#2600)
  [SYCL][NFC] Remove cyclic dependency in headers (intel#2601)
  [SYCL][Doc] Fix Sphinx docs index (intel#2599)
  [SYCL][PI][L0] Add an assert to piEnqueueKernelLaunch() when the GlobalWorkOffset!=0 (intel#2593)
  [SYCL][Driver] Turn on -spirv-allow-extra-diexpressions option (intel#2578)
  [SYCL] Serialize queue related PI API in the Level-Zero plugin (intel#2588)
  Added missing math APIs for devicelib. (intel#2558)
  [SYCL][DOC] Fix path to FPGA device selector (intel#2563)
  [SYCL][CUDA] Add basic sub-group functionality (intel#2587)
  [SYCL] Add specialization constant feature design doc. (intel#2572)
  [SYCL] Expand release lit test to CPU and ACC (intel#2589)
  [SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz (intel#2511)
  [SYCL][ESIMD] Fixed compiler crash in LowerESIMDVecArg pass (intel#2556)
jsji pushed a commit that referenced this pull request May 16, 2024
LLVMExports.cmake from already installed packages references files
from the libllvmlibc package.

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@d2b98fac642a0f6
kbenzie pushed a commit to kbenzie/intel-llvm that referenced this pull request Feb 17, 2025
…mf_preload

Add umf benchmarks: preloaded umfProxy
Chenyang-L pushed a commit that referenced this pull request Feb 18, 2025
…eload

Add umf benchmarks: preloaded umfProxy
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants