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[SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz #2511

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Merged
merged 12 commits into from
Oct 5, 2020

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schittir
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@schittir schittir commented Sep 22, 2020

[[intelfpga::scheduler_target_fmax_mhz(N)]] applies to a device function/lambda function. Indicates that the kernel should be pipelined so as to achieve the specified target clock frequency (Fmax) of N MHz. The argument N may be a template parameter. Limits of N are [0,1048576]; This attribute should be ignored for the FPGA emulator device.

This patch should

  • Add clang support for attribute
  • Add a code-gen test
  • Add a sema/AST test

@schittir schittir requested review from erichkeane and Fznamznon and removed request for erichkeane and Fznamznon September 22, 2020 22:26
@schittir schittir changed the title [SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz [SYCL][WIP] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz Sep 22, 2020
@schittir schittir changed the title [SYCL][WIP] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz [SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz Sep 30, 2020
@schittir schittir marked this pull request as ready for review September 30, 2020 04:11
@schittir schittir force-pushed the scheduler_target_fmax_mhz branch from 5497c7f to 16f34b2 Compare September 30, 2020 05:41
@schittir schittir requested a review from erichkeane September 30, 2020 05:51
@Fznamznon Fznamznon requested a review from mlychkov September 30, 2020 08:36
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Is there any CodeGen changes are coming?
I guess if the attribute is intended to give some information to FPGA backend, we need to add some info to IR as well.

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Is there any CodeGen changes are coming?
I guess if the attribute is intended to give some information to FPGA backend, we need to add some info to IR as well.

Yes. Added a test to show the appropriate IR changes per spec.

@schittir schittir requested a review from Fznamznon September 30, 2020 23:01
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keryell commented Oct 1, 2020

I am scared by looking at all these random attributes landing...
Has anyone explained the pure C++ SYCL philosophy to the FPGA teams working on the programming models?
All these should be provided by some C++ library constructs and these tests like if (TargetFmaxMhz > UpperLimit) should be done there. We cannot have the usual FPGA kitchen sink in the Clang front-end like it is done nowadays in the various FPGA company HLS.
Very unlikely this will be accepted upstream in Clang/LLVM...
While in the FPGA companies the motto is "for any problem we will make a #pragma or an attribute for you" ;-) I think this gives bad publicity for SYCL and FPGA... @mkinsner @jbrodman @Ralender

Not applicable when attribute is not enabled for OpenCL
Handle OpenCL case in a separate pull request if needed
@schittir schittir requested a review from Fznamznon October 1, 2020 19:17
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mkinsner commented Oct 1, 2020

I am scared by looking at all these random attributes landing...
Has anyone explained the pure C++ SYCL philosophy to the FPGA teams working on the programming models?
All these should be provided by some C++ library constructs

Some of the tuning knobs make the most sense as attributes because of where they're attached, but many could also make sense as library abstractions. Everything defined as an attribute so far is a hint, and not a functional assertion / semantic modifier. So it can be argued that these are all pure C++, in that it's safe to ignore them as is usual for unhandled attributes (usually with a warning). Anything that cannot be ignored has intentionally not been defined as an attribute, as far as I know.

Library abstractions are sometimes more invasive than attributes, for example to modify a property of kernel callable. Many of the options to solve that are uglier/more invasive than an attribute. So there is some balance between the two, but a lot of attributes have been defined at this point.

That said, I agree that we should push more to the "library abstraction" style for alignment with C++ philosophy, and for a variety of other reasons. It's important that you're drawing attention to this @keryell. This has revived discussion amongst the people defining these tuning attributes.

Can triSYCL help to motivate a use case where one of these FPGA-specific tuning knobs would be used to target an FPGA, and you would handle without a modified compiler stack (as a lib-only implementation)? That would help to make this case.

Add assert and change test run command
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keryell commented Oct 2, 2020

Can triSYCL help to motivate a use case where one of these FPGA-specific tuning knobs would be used to target an FPGA, and you would handle without a modified compiler stack (as a lib-only implementation)? That would help to make this case.

Thank you for participating to this discussion.
I have not been active enough on this subject but we are back in the business with https://github.com/triSYCL/sycl through our open-source collaboration.
Of course it requires some changes in the compiler stack, but the idea is to remain less invasive.
Some code example with 3 different extensions used: https://github.com/triSYCL/sycl/blob/sycl/unified/master/sycl/test/xocc_tests/edge_detection/edge_detection.cpp#L98
That said, I understand too that some people prefer to use #pragma and attributes as usual too. So probably 2 approaches might be better than only one.

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keryell commented Oct 2, 2020

Please look also to our contribution to mitigate the kitchen sink approach to attributes: https://reviews.llvm.org/D88645

@romanovvlad romanovvlad merged commit 20013e2 into intel:sycl Oct 5, 2020
alexbatashev pushed a commit to alexbatashev/llvm that referenced this pull request Oct 7, 2020
* sycl:
  [SYCL] Fix test failure due to size discrepancy in 32 and 64 bit environment (intel#2594)
  [BuildBot] Linux GPU driver uplift to 20.39.17972 (intel#2600)
  [SYCL][NFC] Remove cyclic dependency in headers (intel#2601)
  [SYCL][Doc] Fix Sphinx docs index (intel#2599)
  [SYCL][PI][L0] Add an assert to piEnqueueKernelLaunch() when the GlobalWorkOffset!=0 (intel#2593)
  [SYCL][Driver] Turn on -spirv-allow-extra-diexpressions option (intel#2578)
  [SYCL] Serialize queue related PI API in the Level-Zero plugin (intel#2588)
  Added missing math APIs for devicelib. (intel#2558)
  [SYCL][DOC] Fix path to FPGA device selector (intel#2563)
  [SYCL][CUDA] Add basic sub-group functionality (intel#2587)
  [SYCL] Add specialization constant feature design doc. (intel#2572)
  [SYCL] Expand release lit test to CPU and ACC (intel#2589)
  [SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz (intel#2511)
  [SYCL][ESIMD] Fixed compiler crash in LowerESIMDVecArg pass (intel#2556)
jsji pushed a commit that referenced this pull request Apr 27, 2024
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7 participants