Skip to content

Conversation

@evgeny-boger
Copy link
Member

H616 core can be clocked at 288 MHz on CPU_PLL without adjusting PLL frequency divider which the kernel doesn't support at the moment.

Running at 288 MHz compared to 488 MHz saves some 0.1W of power.
Update critical temperature to match T507 industrial temperature range.

For thermal throttling we use step-wise throttling optimized for at least 10 years chip lifetime at full load. As the lifetime is limited not only by temperature by also by core voltage, we disallow high core voltage opps at higher core temperatures.
add debug, statistics interfaces and also make trips writable from userspace
@evgeny-boger evgeny-boger requested a review from webconn July 4, 2024 23:44
@webconn webconn mentioned this pull request Jul 5, 2024
@webconn
Copy link
Contributor

webconn commented Jul 5, 2024

rebased in #209

@webconn webconn closed this Jul 5, 2024
@sikmir sikmir deleted the feature/SOFT-3860 branch December 9, 2024 15:46
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants