AMDGPU: Define and Use HasInterpInsts for interp inst definitions

[changpeng]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Changpeng Fang (changpeng)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/84102.diff

3 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+3)
• (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (+4)
• (modified) llvm/lib/Target/AMDGPU/VINTERPInstructions.td (+2-2)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 814ac0b93fcf01..8906c46f279e22 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1877,6 +1877,9 @@ def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
 def HasExpOrExportInsts : Predicate<"Subtarget->hasExpOrExportInsts()">,
   AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
 
+def HasInterpInsts : Predicate<"Subtarget->hasInterpInsts()">,
+  AssemblerPredicate<(all_of FeatureGFX11Insts)>;
+
 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
 
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index bb0ccfce324fd8..3283ac72aa4dd6 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -651,6 +651,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
     return !hasGFX940Insts();
   }
 
+  bool hasInterpInsts() const {
+    return GFX11Insts;
+  }
+
   // DS_ADD_F64/DS_ADD_RTN_F64
   bool hasLdsAtomicAddF64() const { return hasGFX90AInsts(); }
 
diff --git a/llvm/lib/Target/AMDGPU/VINTERPInstructions.td b/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
index f84e163b2df037..0303d1e23a0add 100644
--- a/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VINTERPInstructions.td
@@ -105,7 +105,7 @@ class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
 // VINTERP Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
-let SubtargetPredicate = isGFX11Plus in {
+let SubtargetPredicate = HasInterpInsts in {
 
 let Uses = [M0, EXEC, MODE] in {
 def V_INTERP_P10_F32_inreg : VINTERP_Pseudo <"v_interp_p10_f32", VOP3_VINTERP_F32>;
@@ -123,7 +123,7 @@ def V_INTERP_P2_RTZ_F16_F32_inreg :
   VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
 } // Uses = [M0, EXEC]
 
-} // SubtargetPredicate = isGFX11Plus
+} // SubtargetPredicate = HasInterpInsts.
 
 class VInterpF32Pat <SDPatternOperator op, Instruction inst> : GCNPat <
    (f32 (op

[github-actions]

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff 889d99a50f38150570f6fca903d61ee9770bd932 f815ee4d9f613103f2d18ac98838d12cb42d356a -- llvm/lib/Target/AMDGPU/GCNSubtarget.h

View the diff from clang-format here.

diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 3283ac72aa..475c1b0c3f 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -651,9 +651,7 @@ public:
     return !hasGFX940Insts();
   }
 
-  bool hasInterpInsts() const {
-    return GFX11Insts;
-  }
+  bool hasInterpInsts() const { return GFX11Insts; }
 
   // DS_ADD_F64/DS_ADD_RTN_F64
   bool hasLdsAtomicAddF64() const { return hasGFX90AInsts(); }