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AMDGPU: Define and Use HasInterpInsts for interp inst definitions #84102

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Merged
merged 1 commit into from
Mar 6, 2024
Merged

AMDGPU: Define and Use HasInterpInsts for interp inst definitions #84102

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3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1877,6 +1877,9 @@ def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
def HasExpOrExportInsts : Predicate<"Subtarget->hasExpOrExportInsts()">,
AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;

def HasInterpInsts : Predicate<"Subtarget->hasInterpInsts()">,
AssemblerPredicate<(all_of FeatureGFX11Insts)>;

def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
AssemblerPredicate<(all_of FeatureGFX9Insts)>;

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4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/GCNSubtarget.h
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Expand Up @@ -651,6 +651,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return !hasGFX940Insts();
}

bool hasInterpInsts() const {
return GFX11Insts;
}

// DS_ADD_F64/DS_ADD_RTN_F64
bool hasLdsAtomicAddF64() const { return hasGFX90AInsts(); }

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/VINTERPInstructions.td
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Expand Up @@ -105,7 +105,7 @@ class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
// VINTERP Pseudo Instructions
//===----------------------------------------------------------------------===//

let SubtargetPredicate = isGFX11Plus in {
let SubtargetPredicate = HasInterpInsts in {

let Uses = [M0, EXEC, MODE] in {
def V_INTERP_P10_F32_inreg : VINTERP_Pseudo <"v_interp_p10_f32", VOP3_VINTERP_F32>;
Expand All @@ -123,7 +123,7 @@ def V_INTERP_P2_RTZ_F16_F32_inreg :
VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
} // Uses = [M0, EXEC]

} // SubtargetPredicate = isGFX11Plus
} // SubtargetPredicate = HasInterpInsts.

class VInterpF32Pat <SDPatternOperator op, Instruction inst> : GCNPat <
(f32 (op
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