Search results

[AMDGPU] Optimize image sample followed by llvm.amdgcn.cvt.pkrtz into d16 variant

backend:AMDGPU

llvm:instcombine

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 145203

#145203 In llvm/llvm-project;

· harrisonGPU opened on Jun 22, 2025

AMDGPU: Avoid report_fatal_error on ds ordered intrinsics

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145202

#145202 In llvm/llvm-project;

· arsenm opened on Jun 22, 2025

AMDGPU: Avoid report_fatal_error in image intrinsic lowering

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145201

#145201 In llvm/llvm-project;

· arsenm opened on Jun 22, 2025

AMDGPU: Use reportFatalUsageError for regalloc flag error

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145198

#145198 In llvm/llvm-project;

· arsenm opened on Jun 22, 2025

DAG: Emit an error if trying to legalize read/write register with illegal types

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SystemZ

backend:X86

llvm:codegen

llvm:globalisel

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145197

#145197 In llvm/llvm-project;

· arsenm opened on Jun 22, 2025

CodeGen: Emit error if getRegisterByName fails

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SystemZ

backend:X86

llvm:codegen

llvm:globalisel

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145194

#145194 In llvm/llvm-project;

· arsenm opened on Jun 21, 2025

AMDGPU: Avoid report_fatal_error for unsupported ds_ordered_count

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145172

#145172 In llvm/llvm-project;

· arsenm opened on Jun 21, 2025

[llvm] Optimize misaligned accesses with early profitable splitting

backend:AMDGPU

llvm:codegen

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 145168

#145168 In llvm/llvm-project;

· Acthinks opened on Jun 21, 2025

[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction

backend:AMDGPU

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

llvm:ir

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 145152

#145152 In llvm/llvm-project;

· rampitec opened on Jun 21, 2025

AMDGPU/MC: Try harder to evaluate absolute MC expressions

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145146

#145146 In llvm/llvm-project;

· nhaehnle opened on Jun 21, 2025

AMDGPU: Avoid report_fatal_error for reporting libcalls

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145134

#145134 In llvm/llvm-project;

· arsenm opened on Jun 21, 2025

[AMDGPU] Support merging 16-bit TBUFFER load/store instruction

backend:AMDGPU

Status: Open (in progress).

llvm/llvm-projectnumber 145078

#145078 In llvm/llvm-project;

· harrisonGPU opened on Jun 20, 2025