[AMDGPU] Add new aliases ds_subrev_u32/u64 for ds_rsub_u32/u64 #83118
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Note that the instructions have not been renamed and that there are no corresponding aliases for ds_rsub_rtn_u32/u64. This matches SP3 behavior.
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@llvm/pr-subscribers-mc Author: Jay Foad (jayfoad) ChangesNote that the instructions have not been renamed and that there are no Full diff: https://github.com/llvm/llvm-project/pull/83118.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 515b9476b25b75..074e13317ef89d 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1259,6 +1259,10 @@ defm DS_PK_ADD_RTN_F16 : DS_Real_gfx12<0x0aa>;
defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>;
defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>;
+// New aliases added in GFX12 without renaming the instructions.
+def : MnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">, Requires<[isGFX12Plus]>;
+def : MnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">, Requires<[isGFX12Plus]>;
+
//===----------------------------------------------------------------------===//
// GFX11.
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s b/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
index aa4b028160175c..8b076094aa8581 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
@@ -23,3 +23,9 @@ ds_min_rtn_f32 v5, v1, v2
ds_min_rtn_f64 v[5:6], v1, v[2:3]
// GFX12: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_subrev_u32 v1, v2
+// GFX12: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_subrev_u64 v1, v[2:3]
+// GFX12: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
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@llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) ChangesNote that the instructions have not been renamed and that there are no Full diff: https://github.com/llvm/llvm-project/pull/83118.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 515b9476b25b75..074e13317ef89d 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1259,6 +1259,10 @@ defm DS_PK_ADD_RTN_F16 : DS_Real_gfx12<0x0aa>;
defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>;
defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>;
+// New aliases added in GFX12 without renaming the instructions.
+def : MnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">, Requires<[isGFX12Plus]>;
+def : MnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">, Requires<[isGFX12Plus]>;
+
//===----------------------------------------------------------------------===//
// GFX11.
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s b/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
index aa4b028160175c..8b076094aa8581 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s
@@ -23,3 +23,9 @@ ds_min_rtn_f32 v5, v1, v2
ds_min_rtn_f64 v[5:6], v1, v[2:3]
// GFX12: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_subrev_u32 v1, v2
+// GFX12: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_subrev_u64 v1, v[2:3]
+// GFX12: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
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mbrkusanin
approved these changes
Feb 27, 2024
mbrkusanin
reviewed
Feb 27, 2024
| // GFX12: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00] | ||
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| ds_subrev_u64 v1, v[2:3] | ||
| // GFX12: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00] |
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For these alias tests it makes sense to me to include full output in CHECK lines not just the hex values. That way we can see the other name.
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Agreed. Done. I will go back and fix the existing tests separately.
jayfoad
added a commit
to jayfoad/llvm-project
that referenced
this pull request
Feb 29, 2024
Following on from llvm#83118, this adds aliases for the "rtn" forms of these instructions. The fact that they were missing from SP3 was an oversight which has been fixed now.
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Note that the instructions have not been renamed and that there are no
corresponding aliases for ds_rsub_rtn_u32/u64. This matches SP3
behavior.