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[AMDGPU] Add new aliases ds_subrev_u32/u64 for ds_rsub_u32/u64 (#83118)
Note that the instructions have not been renamed and that there are no corresponding aliases for ds_rsub_rtn_u32/u64. This matches SP3 behavior.
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llvm/lib/Target/AMDGPU/DSInstructions.td

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@@ -1259,6 +1259,10 @@ defm DS_PK_ADD_RTN_F16 : DS_Real_gfx12<0x0aa>;
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defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>;
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defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>;
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// New aliases added in GFX12 without renaming the instructions.
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def : MnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">, Requires<[isGFX12Plus]>;
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def : MnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">, Requires<[isGFX12Plus]>;
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//===----------------------------------------------------------------------===//
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// GFX11.
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//===----------------------------------------------------------------------===//

llvm/test/MC/AMDGPU/gfx12_asm_ds_alias.s

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@@ -23,3 +23,9 @@ ds_min_rtn_f32 v5, v1, v2
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ds_min_rtn_f64 v[5:6], v1, v[2:3]
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// GFX12: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
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ds_subrev_u32 v1, v2
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// GFX12: ds_rsub_u32 v1, v2 ; encoding: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
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ds_subrev_u64 v1, v[2:3]
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// GFX12: ds_rsub_u64 v1, v[2:3] ; encoding: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]

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