[AMDGPU] Rename call instructions from b64 to i64 #145103

rampitec · 2025-06-20T21:13:09Z

These get renamed in gfx1250 and on from B64 to I64:

S_CALL_I64
S_GET_PC_I64
S_RFE_I64
S_SET_PC_I64
S_SWAP_PC_I64

rampitec · 2025-06-20T21:13:29Z

[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction #145152
[AMDGPU] Rename call instructions from b64 to i64 #145103 👈 (View in Graphite)
main

This stack of pull requests is managed by Graphite. Learn more about stacking.

rampitec · 2025-06-20T21:14:21Z

It also adds some basic infrastructure.

github-actions · 2025-06-20T21:16:36Z

✅ With the latest revision this PR passed the C/C++ code formatter.

These get renamed in gfx1250 and on from B64 to I64: S_CALL_I64 S_GET_PC_I64 S_RFE_I64 S_SET_PC_I64 S_SWAP_PC_I64

shiltian · 2025-06-21T13:41:31Z

Is it still a draft?

llvmbot · 2025-06-21T16:36:11Z

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

These get renamed in gfx1250 and on from B64 to I64:

S_CALL_I64
S_GET_PC_I64
S_RFE_I64
S_SET_PC_I64
S_SWAP_PC_I64

Patch is 20.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/145103.diff

12 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+20)
(modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+8)
(modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (+1)
(modified) llvm/lib/Target/AMDGPU/SIDefines.h (+1)
(modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+3)
(modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+26)
(modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+4)
(modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+1)
(added) llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s (+30)
(added) llvm/test/MC/AMDGPU/gfx1250_asm_sopk.s (+9)
(modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt (+36-18)
(modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt (+13-7)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 4b17e1c808b50..ab83cf9e7395a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2244,10 +2244,30 @@ def isGFX12Only :
   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12">,
   AssemblerPredicate<(all_of FeatureGFX12Insts)>;
 
+def isGFX12Not12_50 :
+  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts()">,
+  AssemblerPredicate<(all_of FeatureGFX12Insts, (not FeatureGFX1250Insts))>;
+
 def isGFX12Plus :
   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
   AssemblerPredicate<(all_of FeatureGFX12Insts)>;
 
+def isGFX12PlusNot12_50 :
+  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts()">,
+  AssemblerPredicate<(all_of FeatureGFX12Insts, (not FeatureGFX1250Insts))>;
+
+def isGFX125xOnly :
+  Predicate<"Subtarget->hasGFX1250Insts()">,
+  AssemblerPredicate<(all_of FeatureGFX1250Insts)>;
+
+def isGFX1250Plus :
+  Predicate<"Subtarget->hasGFX1250Insts()">,
+  AssemblerPredicate<(all_of FeatureGFX1250Insts)>;
+
+def isNotGFX1250Plus :
+  Predicate<"!Subtarget->hasGFX1250Insts()">,
+  AssemblerPredicate<(all_of (not FeatureGFX1250Insts))>;
+
 def HasMinimum3Maximum3F32 :
   Predicate<"Subtarget->hasMinimum3Maximum3F32()">,
   AssemblerPredicate<(all_of FeatureMinimum3Maximum3F32)>;
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 349e408b79658..2e891419f0e39 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -717,6 +717,12 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                         Address, CS))
         break;
 
+      // FIXME: Should use DecoderTableGFX1250_FAKE1632, but it is not generated
+      //        yet.
+      if (isGFX1250() &&
+          tryDecodeInst(DecoderTableGFX125032, MI, DW, Address, CS))
+        break;
+
       if (isGFX12() &&
           tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
                         Address, CS))
@@ -2022,6 +2028,8 @@ bool AMDGPUDisassembler::isGFX12Plus() const {
   return AMDGPU::isGFX12Plus(STI);
 }
 
+bool AMDGPUDisassembler::isGFX1250() const { return AMDGPU::isGFX1250(STI); }
+
 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const {
   return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
 }
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index a82dee430e01d..67156b4a3a188 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -230,6 +230,7 @@ class AMDGPUDisassembler : public MCDisassembler {
   bool isGFX11Plus() const;
   bool isGFX12() const;
   bool isGFX12Plus() const;
+  bool isGFX1250() const;
 
   bool hasArchitectedFlatScratch() const;
   bool hasKernargPreload() const;
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 0f603a43fd626..baf74dbdde20e 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -45,6 +45,7 @@ enum {
   GFX940 = 9,
   GFX11 = 10,
   GFX12 = 11,
+  GFX1250 = 12,
 };
 }
 
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 768f57c469d64..53c0635f02bf2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -31,6 +31,7 @@ def SIEncodingFamily {
   int GFX940 = 9;
   int GFX11 = 10;
   int GFX12 = 11;
+  int GFX1250 = 12;
 }
 
 //===----------------------------------------------------------------------===//
@@ -44,6 +45,8 @@ class GFXGen<Predicate pred, string dn, string suffix, int sub> {
   int Subtarget = sub;
 }
 
+def GFX1250Gen       : GFXGen<isGFX125xOnly, "GFX1250", "_gfx1250", SIEncodingFamily.GFX1250>;
+def GFX12Not12_50Gen : GFXGen<isGFX12Not12_50, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
 def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
 def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
 def GFX10Gen : GFXGen<isGFX10Only, "GFX10", "_gfx10", SIEncodingFamily.GFX10>;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 3f2e764f29268..8c739c2760b17 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -2008,6 +2008,15 @@ multiclass SOP1_IMM_Real_gfx12<bits<8> op> {
 multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :
   SOP1_Real_gfx11<op, name>, SOP1_Real_gfx12<op, name>;
 
+multiclass SOP1_Real_gfx1250<bits<8> op, string name = !tolower(NAME)> {
+  defvar ps = !cast<SOP1_Pseudo>(NAME);
+  def _gfx1250 : SOP1_Real<op, ps, name>,
+                 Select<GFX1250Gen, ps.PseudoInstr>;
+  if !ne(ps.Mnemonic, name) then
+    let AssemblerPredicate = isGFX1250Plus in
+    def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
+}
+
 defm S_MOV_B32                    : SOP1_Real_gfx11_gfx12<0x000>;
 defm S_MOV_B64                    : SOP1_Real_gfx11_gfx12<0x001>;
 defm S_CMOV_B32                   : SOP1_Real_gfx11_gfx12<0x002>;
@@ -2066,10 +2075,16 @@ defm S_MOVRELS_B64                : SOP1_Real_gfx11_gfx12<0x041>;
 defm S_MOVRELD_B32                : SOP1_Real_gfx11_gfx12<0x042>;
 defm S_MOVRELD_B64                : SOP1_Real_gfx11_gfx12<0x043>;
 defm S_MOVRELSD_2_B32             : SOP1_Real_gfx11_gfx12<0x044>;
+let OtherPredicates = [isNotGFX1250Plus] in {
 defm S_GETPC_B64                  : SOP1_Real_gfx11_gfx12<0x047>;
 defm S_SETPC_B64                  : SOP1_Real_gfx11_gfx12<0x048>;
 defm S_SWAPPC_B64                 : SOP1_Real_gfx11_gfx12<0x049>;
 defm S_RFE_B64                    : SOP1_Real_gfx11_gfx12<0x04a>;
+}
+defm S_GETPC_B64                  : SOP1_Real_gfx1250<0x047, "s_get_pc_i64">;
+defm S_SETPC_B64                  : SOP1_Real_gfx1250<0x048, "s_set_pc_i64">;
+defm S_SWAPPC_B64                 : SOP1_Real_gfx1250<0x049, "s_swap_pc_i64">;
+defm S_RFE_B64                    : SOP1_Real_gfx1250<0x04a, "s_rfe_i64">;
 defm S_SENDMSG_RTN_B32            : SOP1_Real_gfx11_gfx12<0x04c>;
 defm S_SENDMSG_RTN_B64            : SOP1_Real_gfx11_gfx12<0x04d>;
 defm S_BARRIER_SIGNAL_M0          : SOP1_M0_Real_gfx12<0x04e>;
@@ -2444,10 +2459,21 @@ multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
 multiclass SOPK_Real64_gfx11_gfx12<bits<5> op> :
   SOPK_Real64_gfx11<op>, SOPK_Real64_gfx12<op>;
 
+multiclass SOPK_Real32_gfx1250<bits<5> op, string name = !tolower(NAME)> {
+  defvar ps = !cast<SOPK_Pseudo>(NAME);
+  def _gfx1250 : SOPK_Real32<op, ps, name>,
+                 Select<GFX1250Gen, ps.PseudoInstr>;
+  if !ne(ps.Mnemonic, name) then
+    let AssemblerPredicate = isGFX1250Plus in
+    def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
+}
+
 defm S_GETREG_B32           : SOPK_Real32_gfx11_gfx12<0x011>;
 defm S_SETREG_B32           : SOPK_Real32_gfx11_gfx12<0x012>;
 defm S_SETREG_IMM32_B32     : SOPK_Real64_gfx11_gfx12<0x013>;
+let OtherPredicates = [isNotGFX1250Plus] in
 defm S_CALL_B64             : SOPK_Real32_gfx11_gfx12<0x014>;
+defm S_CALL_B64             : SOPK_Real32_gfx1250<0x014, "s_call_i64">;
 defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>;
 defm S_SUBVECTOR_LOOP_END   : SOPK_Real32_gfx11<0x017>;
 defm S_WAITCNT_VSCNT        : SOPK_Real32_gfx11<0x018>;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index c0cd43a9c35df..47d213d28ff7e 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2233,6 +2233,10 @@ bool isGFX12Plus(const MCSubtargetInfo &STI) { return isGFX12(STI); }
 
 bool isNotGFX12Plus(const MCSubtargetInfo &STI) { return !isGFX12Plus(STI); }
 
+bool isGFX1250(const MCSubtargetInfo &STI) {
+  return STI.getFeatureBits()[AMDGPU::FeatureGFX1250Insts];
+}
+
 bool isNotGFX11Plus(const MCSubtargetInfo &STI) { return !isGFX11Plus(STI); }
 
 bool isNotGFX10Plus(const MCSubtargetInfo &STI) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 975a8908059c1..aa5406370d84b 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1435,6 +1435,7 @@ bool isGFX11(const MCSubtargetInfo &STI);
 bool isGFX11Plus(const MCSubtargetInfo &STI);
 bool isGFX12(const MCSubtargetInfo &STI);
 bool isGFX12Plus(const MCSubtargetInfo &STI);
+bool isGFX1250(const MCSubtargetInfo &STI);
 bool isNotGFX12Plus(const MCSubtargetInfo &STI);
 bool isNotGFX11Plus(const MCSubtargetInfo &STI);
 bool isGCN3Encoding(const MCSubtargetInfo &STI);
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
new file mode 100644
index 0000000000000..95a9268112920
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
@@ -0,0 +1,30 @@
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR --implicit-check-not=error: --strict-whitespace %s
+
+s_get_pc_i64 s[2:3]
+// GFX1250: s_get_pc_i64 s[2:3]                     ; encoding: [0x00,0x47,0x82,0xbe]
+// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_getpc_b64 s[2:3]
+// GFX1250: s_get_pc_i64 s[2:3]                     ; encoding: [0x00,0x47,0x82,0xbe]
+
+s_set_pc_i64 s[2:3]
+// GFX1250: s_set_pc_i64 s[2:3]                     ; encoding: [0x02,0x48,0x80,0xbe]
+// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_setpc_b64 s[2:3]
+// GFX1250: s_set_pc_i64 s[2:3]                     ; encoding: [0x02,0x48,0x80,0xbe]
+
+s_swap_pc_i64 s[2:3], 10
+// GFX1250: s_swap_pc_i64 s[2:3], 10                ; encoding: [0x8a,0x49,0x82,0xbe]
+// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_swappc_b64 s[2:3], 10
+// GFX1250: s_swap_pc_i64 s[2:3], 10                ; encoding: [0x8a,0x49,0x82,0xbe]
+
+s_rfe_i64 s[2:3]
+// GFX1250: s_rfe_i64 s[2:3]                        ; encoding: [0x02,0x4a,0x80,0xbe]
+// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_rfe_b64 s[2:3]
+// GFX1250: s_rfe_i64 s[2:3]                        ; encoding: [0x02,0x4a,0x80,0xbe]
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sopk.s
new file mode 100644
index 0000000000000..0945e0dcc9b85
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sopk.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR --implicit-check-not=error: -strict-whitespace %s
+
+s_call_i64 s[0:1], 4660
+// GFX1250: s_call_i64 s[0:1], 4660                 ; encoding: [0x34,0x12,0x00,0xba]
+// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_call_b64 s[0:1], 4660
+// GFX1250: s_call_i64 s[0:1], 4660                 ; encoding: [0x34,0x12,0x00,0xba]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
index 31f61e48126c1..dd3588d5da015 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
 
 0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00
 # GFX12: s_alloc_vgpr 0x1235                     ; encoding: [0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00]
@@ -2270,16 +2271,20 @@
 # GFX12: s_ctz_i32_b64 vcc_lo, s[2:3]            ; encoding: [0x02,0x09,0xea,0xbe]
 
 0x00,0x47,0xfe,0xbe
-# GFX12: s_getpc_b64 exec                        ; encoding: [0x00,0x47,0xfe,0xbe]
+# GFX1200: s_getpc_b64 exec                        ; encoding: [0x00,0x47,0xfe,0xbe]
+# GFX1250: s_get_pc_i64 exec                       ; encoding: [0x00,0x47,0xfe,0xbe]
 
 0x00,0x47,0x80,0xbe
-# GFX12: s_getpc_b64 s[0:1]                      ; encoding: [0x00,0x47,0x80,0xbe]
+# GFX1200: s_getpc_b64 s[0:1]                      ; encoding: [0x00,0x47,0x80,0xbe]
+# GFX1250: s_get_pc_i64 s[0:1]                     ; encoding: [0x00,0x47,0x80,0xbe]
 
 0x00,0x47,0xe8,0xbe
-# GFX12: s_getpc_b64 s[104:105]                  ; encoding: [0x00,0x47,0xe8,0xbe]
+# GFX1200: s_getpc_b64 s[104:105]                  ; encoding: [0x00,0x47,0xe8,0xbe]
+# GFX1250: s_get_pc_i64 s[104:105]                 ; encoding: [0x00,0x47,0xe8,0xbe]
 
 0x00,0x47,0xea,0xbe
-# GFX12: s_getpc_b64 vcc                         ; encoding: [0x00,0x47,0xea,0xbe]
+# GFX1200: s_getpc_b64 vcc                         ; encoding: [0x00,0x47,0xea,0xbe]
+# GFX1250: s_get_pc_i64 vcc                        ; encoding: [0x00,0x47,0xea,0xbe]
 
 0x01,0x00,0xff,0xbe
 # GFX12: s_mov_b32 exec_hi, s1                   ; encoding: [0x01,0x00,0xff,0xbe]
@@ -3218,13 +3223,16 @@
 # GFX12: s_quadmask_b64 vcc, s[2:3]              ; encoding: [0x02,0x1b,0xea,0xbe]
 
 0x00,0x4a,0x80,0xbe
-# GFX12: s_rfe_b64 s[0:1]                        ; encoding: [0x00,0x4a,0x80,0xbe]
+# GFX1200: s_rfe_b64 s[0:1]                        ; encoding: [0x00,0x4a,0x80,0xbe]
+# GFX1250: s_rfe_i64 s[0:1]                        ; encoding: [0x00,0x4a,0x80,0xbe]
 
 0x68,0x4a,0x80,0xbe
-# GFX12: s_rfe_b64 s[104:105]                    ; encoding: [0x68,0x4a,0x80,0xbe]
+# GFX1200: s_rfe_b64 s[104:105]                    ; encoding: [0x68,0x4a,0x80,0xbe]
+# GFX1250: s_rfe_i64 s[104:105]                    ; encoding: [0x68,0x4a,0x80,0xbe]
 
 0x6a,0x4a,0x80,0xbe
-# GFX12: s_rfe_b64 vcc                           ; encoding: [0x6a,0x4a,0x80,0xbe]
+# GFX1200: s_rfe_b64 vcc                           ; encoding: [0x6a,0x4a,0x80,0xbe]
+# GFX1250: s_rfe_i64 vcc                           ; encoding: [0x6a,0x4a,0x80,0xbe]
 
 0x00,0x4c,0x81,0xbe
 # GFX12: s_sendmsg_rtn_b32 s1, sendmsg(0, 0, 0)  ; encoding: [0x00,0x4c,0x81,0xbe]
@@ -3269,16 +3277,20 @@
 # GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_SE_AID_ID) ; encoding: [0x87,0x4c,0x80,0xbe]
 
 0x00,0x48,0x80,0xbe
-# GFX12: s_setpc_b64 s[0:1]                      ; encoding: [0x00,0x48,0x80,0xbe]
+# GFX1200: s_setpc_b64 s[0:1]                      ; encoding: [0x00,0x48,0x80,0xbe]
+# GFX1250: s_set_pc_i64 s[0:1]                     ; encoding: [0x00,0x48,0x80,0xbe]
 
 0x68,0x48,0x80,0xbe
-# GFX12: s_setpc_b64 s[104:105]                  ; encoding: [0x68,0x48,0x80,0xbe]
+# GFX1200: s_setpc_b64 s[104:105]                  ; encoding: [0x68,0x48,0x80,0xbe]
+# GFX1250: s_set_pc_i64 s[104:105]                 ; encoding: [0x68,0x48,0x80,0xbe]
 
 0x6a,0x48,0x80,0xbe
-# GFX12: s_setpc_b64 vcc                         ; encoding: [0x6a,0x48,0x80,0xbe]
+# GFX1200: s_setpc_b64 vcc                         ; encoding: [0x6a,0x48,0x80,0xbe]
+# GFX1250: s_set_pc_i64 vcc                        ; encoding: [0x6a,0x48,0x80,0xbe]
 
 0xcb,0x48,0xf5,0xbe
-# GFX12: s_setpc_b64 -11/*Invalid immediate*/    ; encoding: [0xf5,0x48,0x80,0xbe]
+# GFX1200: s_setpc_b64 -11/*Invalid immediate*/    ; encoding: [0xf5,0x48,0x80,0xbe]
+# GFX1250: s_set_pc_i64 -11/*Invalid immediate*/   ; encoding: [0xf5,0x48,0x80,0xbe]
 
 0x01,0x0f,0xff,0xbe
 # GFX12: s_sext_i32_i16 exec_hi, s1              ; encoding: [0x01,0x0f,0xff,0xbe]
@@ -3401,22 +3413,28 @@
 # GFX12: s_sext_i32_i8 vcc_lo, s1                ; encoding: [0x01,0x0e,0xea,0xbe]
 
 0x66,0x49,0x80,0xbe
-# GFX12: s_swappc_b64 s[0:1], s[102:103]         ; encoding: [0x66,0x49,0x80,0xbe]
+# GFX1200: s_swappc_b64 s[0:1], s[102:103]         ; encoding: [0x66,0x49,0x80,0xbe]
+# GFX1250: s_swap_pc_i64 s[0:1], s[102:103]        ; encoding: [0x66,0x49,0x80,0xbe]
 
 0x02,0x49,0x80,0xbe
-# GFX12: s_swappc_b64 s[0:1], s[2:3]             ; encoding: [0x02,0x49,0x80,0xbe]
+# GFX1200: s_swappc_b64 s[0:1], s[2:3]             ; encoding: [0x02,0x49,0x80,0xbe]
+# GFX1250: s_swap_pc_i64 s[0:1], s[2:3]            ; encoding: [0x02,0x49,0x80,0xbe]
 
 0x6a,0x49,0x80,0xbe
-# GFX12: s_swappc_b64 s[0:1], vcc                ; encoding: [0x6a,0x49,0x80,0xbe]
+# GFX1200: s_swappc_b64 s[0:1], vcc                ; encoding: [0x6a,0x49,0x80,0xbe]
+# GFX1250: s_swap_pc_i64 s[0:1], vcc               ; encoding: [0x6a,0x49,0x80,0xbe]
 
 0x66,0x49,0xe8,0xbe
-# GFX12: s_swappc_b64 s[104:105], s[102:103]     ; encoding: [0x66,0x49,0xe8,0xbe]
+# GFX1200: s_swappc_b64 s[104:105], s[102:103]     ; encoding: [0x66,0x49,0xe8,0xbe]
+# GFX1250: s_swap_pc_i64 s[104:105], s[102:103]    ; encoding: [0x66,0x49,0xe8,0xbe]
 
 0x02,0x49,0xe8,0xbe
-# GFX12: s_swappc_b64 s[104:105], s[2:3]         ; encoding: [0x02,0x49,0xe8,0xbe]
+# GFX1200: s_swappc_b64 s[104:105], s[2:3]         ; encoding: [0x02,0x49,0xe8,0xbe]
+# GFX1250: s_swap_pc_i64 s[104:105], s[2:3]        ; encoding: [0x02,0x49,0xe8,0xbe]
 
 0x02,0x49,0xea,0xbe
-# GFX12: s_swappc_b64 vcc, s[2:3]                ; encoding: [0x02,0x49,0xea,0xbe]
+# GFX1200: s_swappc_b64 vcc, s[2:3]                ; encoding: [0x02,0x49,0xea,0xbe]
+# GFX1250: s_swap_pc_i64 vcc, s[2:3]               ; encoding: [0x02,0x49,0xea,0xbe]
 
 0x01,0x1c,0xff,0xbe
 # GFX12: s_wqm_b32 exec_hi, s1                   ; encoding: [0x01,0x1c,0xff,0xbe]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
index 3e323ed69216c..49fa263f6bbf8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
@@ -1,5 +1,6 @@
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX12,GFX1200 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX1200 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX12,GFX1250 %s
 
 # GFX12: s_addk_co_i32 exec_hi, 0x1234           ; encoding: [0x34,0x12,0xff,0xb7]
 0x34,0x12,0xff,0xb7
@@ -25,19 +26,24 @@
 # GFX12: s_addk_co_i32 vcc_lo, 0x1234            ; encoding: [0x34,0x12,0xea,0xb7]
 0x34,0x12,0xea,0xb7
 
-# GFX12: s_call_b64 exec, 4660                   ; encoding: [0x34,0x12,0x7e,0xba]
+# GFX1200: s_call_b64 exec, 4660                   ; encoding: [0x34,0x12,0x7e,0xba]
+# GFX1250: s_call_i64 exec, 4660                   ; encoding: [0x34,0x12,0x7e,0xba]
 0x34,0x12,0x7e,0xba
 
-# GFX12: s_call_b64 s[0:1], 4660                 ; encoding: [0x34,0x12,0x00,0xba]
+# GFX1200: s_call_b64 s[0:1], 4660                 ; encoding: [0x34,0x12,0x00,0xba]
+# GFX1250: s_call_i64 s[0:1], 4660                 ; encoding: [0x34,0x12,0x00,0xba]
 0x34,0x12,0x00,0xba
 
-# GFX12: s_call_b64 s[104:105], 4660             ; encoding: [0x34,0x12,0x68,0xba]
+# GFX1200: s_call_b64 s[104:105], 4660             ; encoding: [0x34,0x12,0x68,0xba]
+# GFX1250: s_call_i64 s[104:105], 4660             ; encoding: [0x34,0x12,0x68,0xba]
 0x34,0x12,0x68,0xba
 
-# GFX12: s_call_b64 vcc, 4660                    ; encoding: [0x34,0x12,0x6a,0xba]
+# GFX1200: s_call_b64 vcc, 4660                    ; encoding: [0x34,0x12,0x6a,0xba]
+# GFX1250: s_call_i64 vcc, 4660                    ; encoding: [0x34,0x12,0x6a,0xba]
 0x34,0x12,0x6a,0xba
 
-# GFX12: s_call_b64 null, 4660                   ; encoding: [0x34,0x12,0x7c,0xba]
+# GFX1200: s_call_b64 null, 4660                   ; enco...
[truncated]

rampitec · 2025-06-21T16:36:36Z

Is it still a draft?

No, did not press ready button. Thanks.

rampitec requested review from jayfoad and shiltian June 20, 2025 21:13

rampitec force-pushed the users/rampitec/06-20-_amdgpu_rename_call_instructions_from_b64_to_i64 branch 2 times, most recently from 4dd8e74 to 1930265 Compare June 20, 2025 21:26

[AMDGPU] Rename call instructions from b64 to i64

ac33cc8

These get renamed in gfx1250 and on from B64 to I64: S_CALL_I64 S_GET_PC_I64 S_RFE_I64 S_SET_PC_I64 S_SWAP_PC_I64

rampitec force-pushed the users/rampitec/06-20-_amdgpu_rename_call_instructions_from_b64_to_i64 branch from 1930265 to ac33cc8 Compare June 21, 2025 07:28

rampitec mentioned this pull request Jun 21, 2025

[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction #145152

Merged

rampitec requested a review from arsenm June 21, 2025 07:44

rampitec marked this pull request as ready for review June 21, 2025 16:35

llvmbot added backend:AMDGPU mc Machine (object) code labels Jun 21, 2025

arsenm approved these changes Jun 22, 2025

View reviewed changes

rampitec merged commit fa0b84f into main Jun 22, 2025
11 checks passed

rampitec deleted the users/rampitec/06-20-_amdgpu_rename_call_instructions_from_b64_to_i64 branch June 22, 2025 04:42

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[AMDGPU] Rename call instructions from b64 to i64 #145103

[AMDGPU] Rename call instructions from b64 to i64 #145103

rampitec commented Jun 20, 2025

Uh oh!

rampitec commented Jun 20, 2025 •

edited

Loading

Uh oh!

rampitec commented Jun 20, 2025

Uh oh!

github-actions bot commented Jun 20, 2025 •

edited

Loading

Uh oh!

shiltian commented Jun 21, 2025

Uh oh!

llvmbot commented Jun 21, 2025 •

edited

Loading

Uh oh!

rampitec commented Jun 21, 2025

Uh oh!

Uh oh!

Uh oh!

[AMDGPU] Rename call instructions from b64 to i64 #145103

[AMDGPU] Rename call instructions from b64 to i64 #145103

Conversation

rampitec commented Jun 20, 2025

Uh oh!

rampitec commented Jun 20, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

rampitec commented Jun 20, 2025

Uh oh!

github-actions bot commented Jun 20, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

shiltian commented Jun 21, 2025

Uh oh!

llvmbot commented Jun 21, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

rampitec commented Jun 21, 2025

Uh oh!

Uh oh!

Uh oh!

rampitec commented Jun 20, 2025 •

edited

Loading

github-actions bot commented Jun 20, 2025 •

edited

Loading

llvmbot commented Jun 21, 2025 •

edited

Loading