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[AMDGPU] Rename call instructions from b64 to i64 (#145103)
These get renamed in gfx1250 and on from B64 to I64: S_CALL_I64 S_GET_PC_I64 S_RFE_I64 S_SET_PC_I64 S_SWAP_PC_I64
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+152
-25
lines changed

12 files changed

+152
-25
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2244,10 +2244,30 @@ def isGFX12Only :
22442244
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12">,
22452245
AssemblerPredicate<(all_of FeatureGFX12Insts)>;
22462246

2247+
def isGFX12Not12_50 :
2248+
Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts()">,
2249+
AssemblerPredicate<(all_of FeatureGFX12Insts, (not FeatureGFX1250Insts))>;
2250+
22472251
def isGFX12Plus :
22482252
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
22492253
AssemblerPredicate<(all_of FeatureGFX12Insts)>;
22502254

2255+
def isGFX12PlusNot12_50 :
2256+
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts()">,
2257+
AssemblerPredicate<(all_of FeatureGFX12Insts, (not FeatureGFX1250Insts))>;
2258+
2259+
def isGFX125xOnly :
2260+
Predicate<"Subtarget->hasGFX1250Insts()">,
2261+
AssemblerPredicate<(all_of FeatureGFX1250Insts)>;
2262+
2263+
def isGFX1250Plus :
2264+
Predicate<"Subtarget->hasGFX1250Insts()">,
2265+
AssemblerPredicate<(all_of FeatureGFX1250Insts)>;
2266+
2267+
def isNotGFX1250Plus :
2268+
Predicate<"!Subtarget->hasGFX1250Insts()">,
2269+
AssemblerPredicate<(all_of (not FeatureGFX1250Insts))>;
2270+
22512271
def HasMinimum3Maximum3F32 :
22522272
Predicate<"Subtarget->hasMinimum3Maximum3F32()">,
22532273
AssemblerPredicate<(all_of FeatureMinimum3Maximum3F32)>;

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -717,6 +717,12 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
717717
Address, CS))
718718
break;
719719

720+
// FIXME: Should use DecoderTableGFX1250_FAKE1632, but it is not generated
721+
// yet.
722+
if (isGFX1250() &&
723+
tryDecodeInst(DecoderTableGFX125032, MI, DW, Address, CS))
724+
break;
725+
720726
if (isGFX12() &&
721727
tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
722728
Address, CS))
@@ -2022,6 +2028,8 @@ bool AMDGPUDisassembler::isGFX12Plus() const {
20222028
return AMDGPU::isGFX12Plus(STI);
20232029
}
20242030

2031+
bool AMDGPUDisassembler::isGFX1250() const { return AMDGPU::isGFX1250(STI); }
2032+
20252033
bool AMDGPUDisassembler::hasArchitectedFlatScratch() const {
20262034
return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
20272035
}

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -230,6 +230,7 @@ class AMDGPUDisassembler : public MCDisassembler {
230230
bool isGFX11Plus() const;
231231
bool isGFX12() const;
232232
bool isGFX12Plus() const;
233+
bool isGFX1250() const;
233234

234235
bool hasArchitectedFlatScratch() const;
235236
bool hasKernargPreload() const;

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ enum {
4545
GFX940 = 9,
4646
GFX11 = 10,
4747
GFX12 = 11,
48+
GFX1250 = 12,
4849
};
4950
}
5051

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ def SIEncodingFamily {
3131
int GFX940 = 9;
3232
int GFX11 = 10;
3333
int GFX12 = 11;
34+
int GFX1250 = 12;
3435
}
3536

3637
//===----------------------------------------------------------------------===//
@@ -44,6 +45,8 @@ class GFXGen<Predicate pred, string dn, string suffix, int sub> {
4445
int Subtarget = sub;
4546
}
4647

48+
def GFX1250Gen : GFXGen<isGFX125xOnly, "GFX1250", "_gfx1250", SIEncodingFamily.GFX1250>;
49+
def GFX12Not12_50Gen : GFXGen<isGFX12Not12_50, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
4750
def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
4851
def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
4952
def GFX10Gen : GFXGen<isGFX10Only, "GFX10", "_gfx10", SIEncodingFamily.GFX10>;

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2008,6 +2008,15 @@ multiclass SOP1_IMM_Real_gfx12<bits<8> op> {
20082008
multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :
20092009
SOP1_Real_gfx11<op, name>, SOP1_Real_gfx12<op, name>;
20102010

2011+
multiclass SOP1_Real_gfx1250<bits<8> op, string name = !tolower(NAME)> {
2012+
defvar ps = !cast<SOP1_Pseudo>(NAME);
2013+
def _gfx1250 : SOP1_Real<op, ps, name>,
2014+
Select<GFX1250Gen, ps.PseudoInstr>;
2015+
if !ne(ps.Mnemonic, name) then
2016+
let AssemblerPredicate = isGFX1250Plus in
2017+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
2018+
}
2019+
20112020
defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>;
20122021
defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>;
20132022
defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>;
@@ -2066,10 +2075,16 @@ defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>;
20662075
defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>;
20672076
defm S_MOVRELD_B64 : SOP1_Real_gfx11_gfx12<0x043>;
20682077
defm S_MOVRELSD_2_B32 : SOP1_Real_gfx11_gfx12<0x044>;
2078+
let OtherPredicates = [isNotGFX1250Plus] in {
20692079
defm S_GETPC_B64 : SOP1_Real_gfx11_gfx12<0x047>;
20702080
defm S_SETPC_B64 : SOP1_Real_gfx11_gfx12<0x048>;
20712081
defm S_SWAPPC_B64 : SOP1_Real_gfx11_gfx12<0x049>;
20722082
defm S_RFE_B64 : SOP1_Real_gfx11_gfx12<0x04a>;
2083+
}
2084+
defm S_GETPC_B64 : SOP1_Real_gfx1250<0x047, "s_get_pc_i64">;
2085+
defm S_SETPC_B64 : SOP1_Real_gfx1250<0x048, "s_set_pc_i64">;
2086+
defm S_SWAPPC_B64 : SOP1_Real_gfx1250<0x049, "s_swap_pc_i64">;
2087+
defm S_RFE_B64 : SOP1_Real_gfx1250<0x04a, "s_rfe_i64">;
20732088
defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12<0x04c>;
20742089
defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12<0x04d>;
20752090
defm S_BARRIER_SIGNAL_M0 : SOP1_M0_Real_gfx12<0x04e>;
@@ -2444,10 +2459,21 @@ multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
24442459
multiclass SOPK_Real64_gfx11_gfx12<bits<5> op> :
24452460
SOPK_Real64_gfx11<op>, SOPK_Real64_gfx12<op>;
24462461

2462+
multiclass SOPK_Real32_gfx1250<bits<5> op, string name = !tolower(NAME)> {
2463+
defvar ps = !cast<SOPK_Pseudo>(NAME);
2464+
def _gfx1250 : SOPK_Real32<op, ps, name>,
2465+
Select<GFX1250Gen, ps.PseudoInstr>;
2466+
if !ne(ps.Mnemonic, name) then
2467+
let AssemblerPredicate = isGFX1250Plus in
2468+
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
2469+
}
2470+
24472471
defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>;
24482472
defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>;
24492473
defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>;
2474+
let OtherPredicates = [isNotGFX1250Plus] in
24502475
defm S_CALL_B64 : SOPK_Real32_gfx11_gfx12<0x014>;
2476+
defm S_CALL_B64 : SOPK_Real32_gfx1250<0x014, "s_call_i64">;
24512477
defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>;
24522478
defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>;
24532479
defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>;

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2233,6 +2233,10 @@ bool isGFX12Plus(const MCSubtargetInfo &STI) { return isGFX12(STI); }
22332233

22342234
bool isNotGFX12Plus(const MCSubtargetInfo &STI) { return !isGFX12Plus(STI); }
22352235

2236+
bool isGFX1250(const MCSubtargetInfo &STI) {
2237+
return STI.getFeatureBits()[AMDGPU::FeatureGFX1250Insts];
2238+
}
2239+
22362240
bool isNotGFX11Plus(const MCSubtargetInfo &STI) { return !isGFX11Plus(STI); }
22372241

22382242
bool isNotGFX10Plus(const MCSubtargetInfo &STI) {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1435,6 +1435,7 @@ bool isGFX11(const MCSubtargetInfo &STI);
14351435
bool isGFX11Plus(const MCSubtargetInfo &STI);
14361436
bool isGFX12(const MCSubtargetInfo &STI);
14371437
bool isGFX12Plus(const MCSubtargetInfo &STI);
1438+
bool isGFX1250(const MCSubtargetInfo &STI);
14381439
bool isNotGFX12Plus(const MCSubtargetInfo &STI);
14391440
bool isNotGFX11Plus(const MCSubtargetInfo &STI);
14401441
bool isGCN3Encoding(const MCSubtargetInfo &STI);

‎llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
2+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12-ERR --implicit-check-not=error: --strict-whitespace %s
3+
4+
s_get_pc_i64 s[2:3]
5+
// GFX1250: s_get_pc_i64 s[2:3] ; encoding: [0x00,0x47,0x82,0xbe]
6+
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
7+
8+
s_getpc_b64 s[2:3]
9+
// GFX1250: s_get_pc_i64 s[2:3] ; encoding: [0x00,0x47,0x82,0xbe]
10+
11+
s_set_pc_i64 s[2:3]
12+
// GFX1250: s_set_pc_i64 s[2:3] ; encoding: [0x02,0x48,0x80,0xbe]
13+
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
14+
15+
s_setpc_b64 s[2:3]
16+
// GFX1250: s_set_pc_i64 s[2:3] ; encoding: [0x02,0x48,0x80,0xbe]
17+
18+
s_swap_pc_i64 s[2:3], 10
19+
// GFX1250: s_swap_pc_i64 s[2:3], 10 ; encoding: [0x8a,0x49,0x82,0xbe]
20+
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
21+
22+
s_swappc_b64 s[2:3], 10
23+
// GFX1250: s_swap_pc_i64 s[2:3], 10 ; encoding: [0x8a,0x49,0x82,0xbe]
24+
25+
s_rfe_i64 s[2:3]
26+
// GFX1250: s_rfe_i64 s[2:3] ; encoding: [0x02,0x4a,0x80,0xbe]
27+
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
28+
29+
s_rfe_b64 s[2:3]
30+
// GFX1250: s_rfe_i64 s[2:3] ; encoding: [0x02,0x4a,0x80,0xbe]

‎llvm/test/MC/AMDGPU/gfx1250_asm_sopk.s

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
2+
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR --implicit-check-not=error: -strict-whitespace %s
3+
4+
s_call_i64 s[0:1], 4660
5+
// GFX1250: s_call_i64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba]
6+
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
7+
8+
s_call_b64 s[0:1], 4660
9+
// GFX1250: s_call_i64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba]

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt

Lines changed: 36 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
2-
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
2+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
3+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
34

45
0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00
56
# GFX12: s_alloc_vgpr 0x1235 ; encoding: [0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00]
@@ -2270,16 +2271,20 @@
22702271
# GFX12: s_ctz_i32_b64 vcc_lo, s[2:3] ; encoding: [0x02,0x09,0xea,0xbe]
22712272

22722273
0x00,0x47,0xfe,0xbe
2273-
# GFX12: s_getpc_b64 exec ; encoding: [0x00,0x47,0xfe,0xbe]
2274+
# GFX1200: s_getpc_b64 exec ; encoding: [0x00,0x47,0xfe,0xbe]
2275+
# GFX1250: s_get_pc_i64 exec ; encoding: [0x00,0x47,0xfe,0xbe]
22742276

22752277
0x00,0x47,0x80,0xbe
2276-
# GFX12: s_getpc_b64 s[0:1] ; encoding: [0x00,0x47,0x80,0xbe]
2278+
# GFX1200: s_getpc_b64 s[0:1] ; encoding: [0x00,0x47,0x80,0xbe]
2279+
# GFX1250: s_get_pc_i64 s[0:1] ; encoding: [0x00,0x47,0x80,0xbe]
22772280

22782281
0x00,0x47,0xe8,0xbe
2279-
# GFX12: s_getpc_b64 s[104:105] ; encoding: [0x00,0x47,0xe8,0xbe]
2282+
# GFX1200: s_getpc_b64 s[104:105] ; encoding: [0x00,0x47,0xe8,0xbe]
2283+
# GFX1250: s_get_pc_i64 s[104:105] ; encoding: [0x00,0x47,0xe8,0xbe]
22802284

22812285
0x00,0x47,0xea,0xbe
2282-
# GFX12: s_getpc_b64 vcc ; encoding: [0x00,0x47,0xea,0xbe]
2286+
# GFX1200: s_getpc_b64 vcc ; encoding: [0x00,0x47,0xea,0xbe]
2287+
# GFX1250: s_get_pc_i64 vcc ; encoding: [0x00,0x47,0xea,0xbe]
22832288

22842289
0x01,0x00,0xff,0xbe
22852290
# GFX12: s_mov_b32 exec_hi, s1 ; encoding: [0x01,0x00,0xff,0xbe]
@@ -3218,13 +3223,16 @@
32183223
# GFX12: s_quadmask_b64 vcc, s[2:3] ; encoding: [0x02,0x1b,0xea,0xbe]
32193224

32203225
0x00,0x4a,0x80,0xbe
3221-
# GFX12: s_rfe_b64 s[0:1] ; encoding: [0x00,0x4a,0x80,0xbe]
3226+
# GFX1200: s_rfe_b64 s[0:1] ; encoding: [0x00,0x4a,0x80,0xbe]
3227+
# GFX1250: s_rfe_i64 s[0:1] ; encoding: [0x00,0x4a,0x80,0xbe]
32223228

32233229
0x68,0x4a,0x80,0xbe
3224-
# GFX12: s_rfe_b64 s[104:105] ; encoding: [0x68,0x4a,0x80,0xbe]
3230+
# GFX1200: s_rfe_b64 s[104:105] ; encoding: [0x68,0x4a,0x80,0xbe]
3231+
# GFX1250: s_rfe_i64 s[104:105] ; encoding: [0x68,0x4a,0x80,0xbe]
32253232

32263233
0x6a,0x4a,0x80,0xbe
3227-
# GFX12: s_rfe_b64 vcc ; encoding: [0x6a,0x4a,0x80,0xbe]
3234+
# GFX1200: s_rfe_b64 vcc ; encoding: [0x6a,0x4a,0x80,0xbe]
3235+
# GFX1250: s_rfe_i64 vcc ; encoding: [0x6a,0x4a,0x80,0xbe]
32283236

32293237
0x00,0x4c,0x81,0xbe
32303238
# GFX12: s_sendmsg_rtn_b32 s1, sendmsg(0, 0, 0) ; encoding: [0x00,0x4c,0x81,0xbe]
@@ -3269,16 +3277,20 @@
32693277
# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_SE_AID_ID) ; encoding: [0x87,0x4c,0x80,0xbe]
32703278

32713279
0x00,0x48,0x80,0xbe
3272-
# GFX12: s_setpc_b64 s[0:1] ; encoding: [0x00,0x48,0x80,0xbe]
3280+
# GFX1200: s_setpc_b64 s[0:1] ; encoding: [0x00,0x48,0x80,0xbe]
3281+
# GFX1250: s_set_pc_i64 s[0:1] ; encoding: [0x00,0x48,0x80,0xbe]
32733282

32743283
0x68,0x48,0x80,0xbe
3275-
# GFX12: s_setpc_b64 s[104:105] ; encoding: [0x68,0x48,0x80,0xbe]
3284+
# GFX1200: s_setpc_b64 s[104:105] ; encoding: [0x68,0x48,0x80,0xbe]
3285+
# GFX1250: s_set_pc_i64 s[104:105] ; encoding: [0x68,0x48,0x80,0xbe]
32763286

32773287
0x6a,0x48,0x80,0xbe
3278-
# GFX12: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
3288+
# GFX1200: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
3289+
# GFX1250: s_set_pc_i64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
32793290

32803291
0xcb,0x48,0xf5,0xbe
3281-
# GFX12: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
3292+
# GFX1200: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
3293+
# GFX1250: s_set_pc_i64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
32823294

32833295
0x01,0x0f,0xff,0xbe
32843296
# GFX12: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
@@ -3401,22 +3413,28 @@
34013413
# GFX12: s_sext_i32_i8 vcc_lo, s1 ; encoding: [0x01,0x0e,0xea,0xbe]
34023414

34033415
0x66,0x49,0x80,0xbe
3404-
# GFX12: s_swappc_b64 s[0:1], s[102:103] ; encoding: [0x66,0x49,0x80,0xbe]
3416+
# GFX1200: s_swappc_b64 s[0:1], s[102:103] ; encoding: [0x66,0x49,0x80,0xbe]
3417+
# GFX1250: s_swap_pc_i64 s[0:1], s[102:103] ; encoding: [0x66,0x49,0x80,0xbe]
34053418

34063419
0x02,0x49,0x80,0xbe
3407-
# GFX12: s_swappc_b64 s[0:1], s[2:3] ; encoding: [0x02,0x49,0x80,0xbe]
3420+
# GFX1200: s_swappc_b64 s[0:1], s[2:3] ; encoding: [0x02,0x49,0x80,0xbe]
3421+
# GFX1250: s_swap_pc_i64 s[0:1], s[2:3] ; encoding: [0x02,0x49,0x80,0xbe]
34083422

34093423
0x6a,0x49,0x80,0xbe
3410-
# GFX12: s_swappc_b64 s[0:1], vcc ; encoding: [0x6a,0x49,0x80,0xbe]
3424+
# GFX1200: s_swappc_b64 s[0:1], vcc ; encoding: [0x6a,0x49,0x80,0xbe]
3425+
# GFX1250: s_swap_pc_i64 s[0:1], vcc ; encoding: [0x6a,0x49,0x80,0xbe]
34113426

34123427
0x66,0x49,0xe8,0xbe
3413-
# GFX12: s_swappc_b64 s[104:105], s[102:103] ; encoding: [0x66,0x49,0xe8,0xbe]
3428+
# GFX1200: s_swappc_b64 s[104:105], s[102:103] ; encoding: [0x66,0x49,0xe8,0xbe]
3429+
# GFX1250: s_swap_pc_i64 s[104:105], s[102:103] ; encoding: [0x66,0x49,0xe8,0xbe]
34143430

34153431
0x02,0x49,0xe8,0xbe
3416-
# GFX12: s_swappc_b64 s[104:105], s[2:3] ; encoding: [0x02,0x49,0xe8,0xbe]
3432+
# GFX1200: s_swappc_b64 s[104:105], s[2:3] ; encoding: [0x02,0x49,0xe8,0xbe]
3433+
# GFX1250: s_swap_pc_i64 s[104:105], s[2:3] ; encoding: [0x02,0x49,0xe8,0xbe]
34173434

34183435
0x02,0x49,0xea,0xbe
3419-
# GFX12: s_swappc_b64 vcc, s[2:3] ; encoding: [0x02,0x49,0xea,0xbe]
3436+
# GFX1200: s_swappc_b64 vcc, s[2:3] ; encoding: [0x02,0x49,0xea,0xbe]
3437+
# GFX1250: s_swap_pc_i64 vcc, s[2:3] ; encoding: [0x02,0x49,0xea,0xbe]
34203438

34213439
0x01,0x1c,0xff,0xbe
34223440
# GFX12: s_wqm_b32 exec_hi, s1 ; encoding: [0x01,0x1c,0xff,0xbe]

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
1-
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s
2-
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s
1+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX12,GFX1200 %s
2+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX1200 %s
3+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX12,GFX1250 %s
34

45
# GFX12: s_addk_co_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
56
0x34,0x12,0xff,0xb7
@@ -25,19 +26,24 @@
2526
# GFX12: s_addk_co_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0xea,0xb7]
2627
0x34,0x12,0xea,0xb7
2728

28-
# GFX12: s_call_b64 exec, 4660 ; encoding: [0x34,0x12,0x7e,0xba]
29+
# GFX1200: s_call_b64 exec, 4660 ; encoding: [0x34,0x12,0x7e,0xba]
30+
# GFX1250: s_call_i64 exec, 4660 ; encoding: [0x34,0x12,0x7e,0xba]
2931
0x34,0x12,0x7e,0xba
3032

31-
# GFX12: s_call_b64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba]
33+
# GFX1200: s_call_b64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba]
34+
# GFX1250: s_call_i64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba]
3235
0x34,0x12,0x00,0xba
3336

34-
# GFX12: s_call_b64 s[104:105], 4660 ; encoding: [0x34,0x12,0x68,0xba]
37+
# GFX1200: s_call_b64 s[104:105], 4660 ; encoding: [0x34,0x12,0x68,0xba]
38+
# GFX1250: s_call_i64 s[104:105], 4660 ; encoding: [0x34,0x12,0x68,0xba]
3539
0x34,0x12,0x68,0xba
3640

37-
# GFX12: s_call_b64 vcc, 4660 ; encoding: [0x34,0x12,0x6a,0xba]
41+
# GFX1200: s_call_b64 vcc, 4660 ; encoding: [0x34,0x12,0x6a,0xba]
42+
# GFX1250: s_call_i64 vcc, 4660 ; encoding: [0x34,0x12,0x6a,0xba]
3843
0x34,0x12,0x6a,0xba
3944

40-
# GFX12: s_call_b64 null, 4660 ; encoding: [0x34,0x12,0x7c,0xba]
45+
# GFX1200: s_call_b64 null, 4660 ; encoding: [0x34,0x12,0x7c,0xba]
46+
# GFX1250: s_call_i64 null, 4660 ; encoding: [0x34,0x12,0x7c,0xba]
4147
0x34,0x12,0x7c,0xba
4248

4349
# GFX12: s_cmovk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb1]

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