[RISCV] Add Smdbltrp and Ssdbltrp extension #111837

T-Tie · 2024-10-10T13:40:51Z

Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) : https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc
Specification link(Ssdbltrp) : https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc

github-actions · 2024-10-10T13:41:11Z

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llvmbot · 2024-10-10T13:41:44Z

@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-clang

@llvm/pr-subscribers-mc

Author: T-Tie (T-Tie)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/111837.diff

7 Files Affected:

(modified) clang/test/Preprocessor/riscv-target-features.c (+18)
(modified) llvm/docs/RISCVUsage.rst (+2)
(modified) llvm/docs/ReleaseNotes.md (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+8)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+6)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+2)

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 05a8534ba13da1..d25f96b66a052a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -29,6 +29,7 @@
 // CHECK-NOT: __riscv_smaia {{.*$}}
 // CHECK-NOT: __riscv_smcdeleg {{.*$}}
 // CHECK-NOT: __riscv_smcsrind {{.*$}}
+// CHECK-NOT: __riscv_smdbltrp {{.*$}}
 // CHECK-NOT: __riscv_smepmp {{.*$}}
 // CHECK-NOT: __riscv_smstateen {{.*$}}
 // CHECK-NOT: __riscv_ssaia {{.*$}}
@@ -37,6 +38,7 @@
 // CHECK-NOT: __riscv_sscofpmf {{.*$}}
 // CHECK-NOT: __riscv_sscounterenw {{.*$}}
 // CHECK-NOT: __riscv_sscsrind {{.*$}}
+// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
 // CHECK-NOT: __riscv_ssqosid{{.*$}}
 // CHECK-NOT: __riscv_ssstateen {{.*$}}
 // CHECK-NOT: __riscv_ssstrict {{.*$}}
@@ -1425,6 +1427,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
 // CHECK-SSCSRIND-EXT: __riscv_sscsrind  1000000{{$}}
 
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32ismdbltrp1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64ismdbltrp1p0 -E -dM %s \
+// RUN:   -o   | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp  1000000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32issdbltrp1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64issdbltrp1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
+// CHECK-SSDBLTRP-EXT: __riscv_ssdbltrp  1000000{{$}}
+
 // RUN: %clang --target=riscv32 \
 // RUN:   -march=rv32i_ssqosid1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5736f3807f131b..4780c20416c165 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -128,6 +128,7 @@ on support follow.
      ``Smaia``         Supported
      ``Smcdeleg``      Supported
      ``Smcsrind``      Supported
+     ``Smdbltrp``      Supported
      ``Smepmp``        Supported
      ``Smstateen``     Assembly Support
      ``Ssaia``         Supported
@@ -136,6 +137,7 @@ on support follow.
      ``Sscofpmf``      Assembly Support
      ``Sscounterenw``  Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
      ``Sscsrind``      Supported
+     ``Ssdbltrp``      Supported
      ``Ssqosid``       Assembly Support
      ``Ssstateen``     Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
      ``Ssstrict``      Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 8ac5900a7e532e..5b77afe148713a 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -158,6 +158,7 @@ Changes to the RISC-V Backend
 * Added `Smctr` and `Ssctr` extensions.
 * `-mcpu=syntacore-scr7` was added.
 * The `Zacas` extension is no longer marked as experimental.
+* Added Smdbltrp, Ssdbltrp extensions to -march.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3d0e1dae801d39..fc93f7c3e1fea1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -927,6 +927,13 @@ def FeatureStdExtSscsrind
     : RISCVExtension<"sscsrind", 1, 0,
                      "'Sscsrind' (Indirect CSR Access Supervisor Level)">;
 
+def FeatureStdExtSmdbltrp
+    : RISCVExtension<"smdbltrp", 1, 0,
+                     "'Smdbltrp' (Double Trap Machine Level)">;
+def FeatureStdExtSsdbltrp
+    : RISCVExtension<"ssdbltrp", 1, 0,
+                     "'Ssdbltrp' (Double Trap Supervisor Level)">;
+
 def FeatureStdExtSmepmp
     : RISCVExtension<"smepmp", 1, 0,
                      "'Smepmp' (Enhanced Physical Memory Protection)">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 86ce368bc1db66..b8f97ae0930a15 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -115,6 +115,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
 ; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
+; RUN: llc -mtriple=riscv32 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMDBLTRP %s
+; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
@@ -258,6 +260,8 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
+; RUN: llc -mtriple=riscv64 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMDBLTRP %s
+; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
@@ -407,6 +411,8 @@
 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 ; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
 ; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
+; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
+; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
 ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
 ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
@@ -548,6 +554,8 @@
 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 ; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
 ; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
+; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
+; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
 ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
 ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 1c0b2a59d0693f..8d9d3ac7132431 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -321,6 +321,12 @@
 .attribute arch, "rv32i_sscsrind1p0"
 # CHECK: attribute      5, "rv32i2p1_sscsrind1p0"
 
+.attribute arch, "rv32i_smdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_smdbltrp1p0"
+
+.attribute arch, "rv32i_ssdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_ssdbltrp1p0"
+
 .attribute arch, "rv32i_smcdeleg1p0"
 # CHECK: attribute      5, "rv32i2p1_smcdeleg1p0"
 
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 33944b64dc1577..f2e16ac0ac93fb 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1064,6 +1064,7 @@ R"(All available -march extensions for RISC-V
     smaia                1.0
     smcdeleg             1.0
     smcsrind             1.0
+    smdbltrp             1.0
     smepmp               1.0
     smstateen            1.0
     ssaia                1.0
@@ -1072,6 +1073,7 @@ R"(All available -march extensions for RISC-V
     sscofpmf             1.0
     sscounterenw         1.0
     sscsrind             1.0
+    ssdbltrp             1.0
     ssqosid              1.0
     ssstateen            1.0
     ssstrict             1.0

llvmbot · 2024-10-10T13:41:45Z

@llvm/pr-subscribers-backend-risc-v

Author: T-Tie (T-Tie)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/111837.diff

7 Files Affected:

(modified) clang/test/Preprocessor/riscv-target-features.c (+18)
(modified) llvm/docs/RISCVUsage.rst (+2)
(modified) llvm/docs/ReleaseNotes.md (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+8)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+6)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+2)

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 05a8534ba13da1..d25f96b66a052a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -29,6 +29,7 @@
 // CHECK-NOT: __riscv_smaia {{.*$}}
 // CHECK-NOT: __riscv_smcdeleg {{.*$}}
 // CHECK-NOT: __riscv_smcsrind {{.*$}}
+// CHECK-NOT: __riscv_smdbltrp {{.*$}}
 // CHECK-NOT: __riscv_smepmp {{.*$}}
 // CHECK-NOT: __riscv_smstateen {{.*$}}
 // CHECK-NOT: __riscv_ssaia {{.*$}}
@@ -37,6 +38,7 @@
 // CHECK-NOT: __riscv_sscofpmf {{.*$}}
 // CHECK-NOT: __riscv_sscounterenw {{.*$}}
 // CHECK-NOT: __riscv_sscsrind {{.*$}}
+// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
 // CHECK-NOT: __riscv_ssqosid{{.*$}}
 // CHECK-NOT: __riscv_ssstateen {{.*$}}
 // CHECK-NOT: __riscv_ssstrict {{.*$}}
@@ -1425,6 +1427,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
 // CHECK-SSCSRIND-EXT: __riscv_sscsrind  1000000{{$}}
 
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32ismdbltrp1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64ismdbltrp1p0 -E -dM %s \
+// RUN:   -o   | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp  1000000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32issdbltrp1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64issdbltrp1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
+// CHECK-SSDBLTRP-EXT: __riscv_ssdbltrp  1000000{{$}}
+
 // RUN: %clang --target=riscv32 \
 // RUN:   -march=rv32i_ssqosid1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5736f3807f131b..4780c20416c165 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -128,6 +128,7 @@ on support follow.
      ``Smaia``         Supported
      ``Smcdeleg``      Supported
      ``Smcsrind``      Supported
+     ``Smdbltrp``      Supported
      ``Smepmp``        Supported
      ``Smstateen``     Assembly Support
      ``Ssaia``         Supported
@@ -136,6 +137,7 @@ on support follow.
      ``Sscofpmf``      Assembly Support
      ``Sscounterenw``  Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
      ``Sscsrind``      Supported
+     ``Ssdbltrp``      Supported
      ``Ssqosid``       Assembly Support
      ``Ssstateen``     Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
      ``Ssstrict``      Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 8ac5900a7e532e..5b77afe148713a 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -158,6 +158,7 @@ Changes to the RISC-V Backend
 * Added `Smctr` and `Ssctr` extensions.
 * `-mcpu=syntacore-scr7` was added.
 * The `Zacas` extension is no longer marked as experimental.
+* Added Smdbltrp, Ssdbltrp extensions to -march.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3d0e1dae801d39..fc93f7c3e1fea1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -927,6 +927,13 @@ def FeatureStdExtSscsrind
     : RISCVExtension<"sscsrind", 1, 0,
                      "'Sscsrind' (Indirect CSR Access Supervisor Level)">;
 
+def FeatureStdExtSmdbltrp
+    : RISCVExtension<"smdbltrp", 1, 0,
+                     "'Smdbltrp' (Double Trap Machine Level)">;
+def FeatureStdExtSsdbltrp
+    : RISCVExtension<"ssdbltrp", 1, 0,
+                     "'Ssdbltrp' (Double Trap Supervisor Level)">;
+
 def FeatureStdExtSmepmp
     : RISCVExtension<"smepmp", 1, 0,
                      "'Smepmp' (Enhanced Physical Memory Protection)">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 86ce368bc1db66..b8f97ae0930a15 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -115,6 +115,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
 ; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
+; RUN: llc -mtriple=riscv32 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMDBLTRP %s
+; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
 ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
@@ -258,6 +260,8 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
+; RUN: llc -mtriple=riscv64 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMDBLTRP %s
+; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
 ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
@@ -407,6 +411,8 @@
 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 ; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
 ; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
+; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
+; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
 ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
 ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
@@ -548,6 +554,8 @@
 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 ; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
 ; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
+; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
+; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
 ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
 ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 1c0b2a59d0693f..8d9d3ac7132431 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -321,6 +321,12 @@
 .attribute arch, "rv32i_sscsrind1p0"
 # CHECK: attribute      5, "rv32i2p1_sscsrind1p0"
 
+.attribute arch, "rv32i_smdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_smdbltrp1p0"
+
+.attribute arch, "rv32i_ssdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_ssdbltrp1p0"
+
 .attribute arch, "rv32i_smcdeleg1p0"
 # CHECK: attribute      5, "rv32i2p1_smcdeleg1p0"
 
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 33944b64dc1577..f2e16ac0ac93fb 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1064,6 +1064,7 @@ R"(All available -march extensions for RISC-V
     smaia                1.0
     smcdeleg             1.0
     smcsrind             1.0
+    smdbltrp             1.0
     smepmp               1.0
     smstateen            1.0
     ssaia                1.0
@@ -1072,6 +1073,7 @@ R"(All available -march extensions for RISC-V
     sscofpmf             1.0
     sscounterenw         1.0
     sscsrind             1.0
+    ssdbltrp             1.0
     ssqosid              1.0
     ssstateen            1.0
     ssstrict             1.0

dtcxzyw

Personally I don't like to add a privileged extension if it doesn't introduce new CSRs/instructions.

asb · 2024-10-10T14:38:08Z

Personally I don't like to add a privileged extension if it doesn't introduce new CSRs/instructions.

I'd actually put that on the agenda for today's sync-up call already. We did add the ones that are in the profiles. I could see an argument for supporting everything as people can then have a -march string that fully describes the target and don't need to go and sort through which options to drop as they don't affect the compiler. But I also see a counter-argument. I'll summarise anything relevant from the sync-up call discussion here.

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asb · 2024-10-10T15:47:16Z

Personally I don't like to add a privileged extension if it doesn't introduce new CSRs/instructions.

I'd actually put that on the agenda for today's sync-up call already. We did add the ones that are in the profiles. I could see an argument for supporting everything as people can then have a -march string that fully describes the target and don't need to go and sort through which options to drop as they don't affect the compiler. But I also see a counter-argument. I'll summarise anything relevant from the sync-up call discussion here.

The conclusion was that nobody present saw a real argument against, feeling "why not" and as I mentioned above, it means people can just match the -march string to their CPU data sheet. Did you have a particular reason against adding such extensions?

topperc · 2024-10-10T16:48:45Z

Personally I don't like to add a privileged extension if it doesn't introduce new CSRs/instructions.

I'd actually put that on the agenda for today's sync-up call already. We did add the ones that are in the profiles. I could see an argument for supporting everything as people can then have a -march string that fully describes the target and don't need to go and sort through which options to drop as they don't affect the compiler. But I also see a counter-argument. I'll summarise anything relevant from the sync-up call discussion here.

The conclusion was that nobody present saw a real argument against, feeling "why not" and as I mentioned above, it means people can just match the -march string to their CPU data sheet. Did you have a particular reason against adding such extensions?

Our hardware build generates a configuration file with a full -march string based on all extensions present in the RTL which we deliver to our customers. So I would like all extensions to be supported otherwise I have to do it downstream.

dtcxzyw · 2024-10-11T00:48:06Z

Personally I don't like to add a privileged extension if it doesn't introduce new CSRs/instructions.

I'd actually put that on the agenda for today's sync-up call already. We did add the ones that are in the profiles. I could see an argument for supporting everything as people can then have a -march string that fully describes the target and don't need to go and sort through which options to drop as they don't affect the compiler. But I also see a counter-argument. I'll summarise anything relevant from the sync-up call discussion here.

The conclusion was that nobody present saw a real argument against, feeling "why not" and as I mentioned above, it means people can just match the -march string to their CPU data sheet. Did you have a particular reason against adding such extensions?

Our hardware build generates a configuration file with a full -march string based on all extensions present in the RTL which we deliver to our customers. So I would like all extensions to be supported otherwise I have to do it downstream.

Make sense to me. No strong objection.

dtcxzyw · 2024-10-11T01:01:02Z

Failed Tests (2):
Clang :: Driver/print-supported-extensions-riscv.c
Clang :: Preprocessor/riscv-target-features.c

dtcxzyw

LGTM.

dtcxzyw · 2024-10-25T07:38:45Z

@T-Tie
Can you fill in the PR description? Then I will merge this patch :)

topperc · 2024-10-29T00:55:18Z

@T-Tie can you pull from main and fix the conflicts?

topperc

LGTM

github-actions · 2024-11-08T07:02:10Z

@T-Tie Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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Smdbltrp and Ssdbltrp supports are added in this PR. Specification link(Smdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url) Specification link(Ssdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)

llvmbot added clang Clang issues not falling into any other category backend:RISC-V mc Machine (object) code labels Oct 10, 2024

dtcxzyw requested review from wangpc-pp, asb, preames and topperc October 10, 2024 14:15

dtcxzyw reviewed Oct 10, 2024

View reviewed changes

llvmbot added the clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' label Oct 11, 2024

dtcxzyw approved these changes Oct 18, 2024

View reviewed changes

T-Tie and others added 9 commits October 24, 2024 16:09

Update riscv-target-features.c double-trap

23aec55

Update RISCVUsage.rst double-trap

481ac24

Update RISCVFeatures.td double-trap

709c7f7

Update attributes.ll double-trap

3f503ce

Update attribute-arch.s double-trap

2c9beb2

Update RISCVISAInfoTest.cpp double-trap

834c528

Update ReleaseNotes.md double-trap

f90a7bf

Update riscv-target-features.c double-trap

a25f112

Update print-supported-extensions-riscv.c double-trap

7a98c63

T-Tie force-pushed the main branch from 0dc9c14 to 7a98c63 Compare October 24, 2024 08:09

Merge branch 'llvm:main' into main

a862400

Merge branch 'main' into main

a529c9c

topperc approved these changes Nov 7, 2024

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Merge branch 'llvm:main' into main

bf864d5

dtcxzyw merged commit c17a914 into llvm:main Nov 8, 2024
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[RISCV] Add Smdbltrp and Ssdbltrp extension #111837

[RISCV] Add Smdbltrp and Ssdbltrp extension #111837

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[RISCV] Add Smdbltrp and Ssdbltrp extension #111837

[RISCV] Add Smdbltrp and Ssdbltrp extension #111837

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