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Merged
merged 12 commits into from
Nov 8, 2024
Merged

[RISCV] Add Smdbltrp and Ssdbltrp extension #111837

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23aec55
Update riscv-target-features.c double-trap
T-Tie Oct 10, 2024
481ac24
Update RISCVUsage.rst double-trap
T-Tie Oct 10, 2024
709c7f7
Update RISCVFeatures.td double-trap
T-Tie Oct 10, 2024
3f503ce
Update attributes.ll double-trap
T-Tie Oct 10, 2024
2c9beb2
Update attribute-arch.s double-trap
T-Tie Oct 10, 2024
834c528
Update RISCVISAInfoTest.cpp double-trap
T-Tie Oct 10, 2024
f90a7bf
Update ReleaseNotes.md double-trap
T-Tie Oct 10, 2024
a25f112
Update riscv-target-features.c double-trap
T-Tie Oct 11, 2024
7a98c63
Update print-supported-extensions-riscv.c double-trap
T-Tie Oct 11, 2024
a862400
Merge branch 'llvm:main' into main
T-Tie Oct 25, 2024
a529c9c
Merge branch 'main' into main
T-Tie Nov 7, 2024
bf864d5
Merge branch 'llvm:main' into main
T-Tie Nov 8, 2024
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2 changes: 2 additions & 0 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -120,6 +120,7 @@
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
Expand All @@ -131,6 +132,7 @@
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level)
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
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18 changes: 18 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -30,6 +30,7 @@
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smrnmi {{.*$}}
// CHECK-NOT: __riscv_smstateen {{.*$}}
Expand All @@ -39,6 +40,7 @@
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
// CHECK-NOT: __riscv_sscounterenw {{.*$}}
// CHECK-NOT: __riscv_sscsrind {{.*$}}
// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
// CHECK-NOT: __riscv_ssstateen {{.*$}}
// CHECK-NOT: __riscv_ssstrict {{.*$}}
Expand Down Expand Up @@ -1444,6 +1446,22 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
// CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismdbltrp1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismdbltrp1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32issdbltrp1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64issdbltrp1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
// CHECK-SSDBLTRP-EXT: __riscv_ssdbltrp 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
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2 changes: 2 additions & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -129,6 +129,7 @@ on support follow.
``Smaia`` Supported
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smdbltrp`` Supported
``Smepmp`` Supported
``Smmpm`` Supported
``Smnpm`` Supported
Expand All @@ -140,6 +141,7 @@ on support follow.
``Sscofpmf`` Assembly Support
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sscsrind`` Supported
``Ssdbltrp`` Supported
``Ssnpm`` Supported
``Sspm`` Supported
``Ssqosid`` Assembly Support
Expand Down
1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -186,6 +186,7 @@ Changes to the RISC-V Backend
* Added `Smctr`, `Ssctr` and `Svvptc` extensions.
* `-mcpu=syntacore-scr7` was added.
* The `Zacas` extension is no longer marked as experimental.
* Added Smdbltrp, Ssdbltrp extensions to -march.
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
are no longer marked as experimental.
* The `Sha` extension is now supported.
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -936,6 +936,13 @@ def FeatureStdExtSscsrind
: RISCVExtension<"sscsrind", 1, 0,
"'Sscsrind' (Indirect CSR Access Supervisor Level)">;

def FeatureStdExtSmdbltrp
: RISCVExtension<"smdbltrp", 1, 0,
"'Smdbltrp' (Double Trap Machine Level)">;
def FeatureStdExtSsdbltrp
: RISCVExtension<"ssdbltrp", 1, 0,
"'Ssdbltrp' (Double Trap Supervisor Level)">;

def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0,
"'Smepmp' (Enhanced Physical Memory Protection)">;
Expand Down
8 changes: 8 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -117,6 +117,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
; RUN: llc -mtriple=riscv32 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMDBLTRP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
Expand Down Expand Up @@ -263,6 +265,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
; RUN: llc -mtriple=riscv64 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMDBLTRP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
Expand Down Expand Up @@ -415,6 +419,8 @@
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
Expand Down Expand Up @@ -559,6 +565,8 @@
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -321,6 +321,12 @@
.attribute arch, "rv32i_sscsrind1p0"
# CHECK: attribute 5, "rv32i2p1_sscsrind1p0"

.attribute arch, "rv32i_smdbltrp1p0"
# CHECK: attribute 5, "rv32i2p1_smdbltrp1p0"

.attribute arch, "rv32i_ssdbltrp1p0"
# CHECK: attribute 5, "rv32i2p1_ssdbltrp1p0"

.attribute arch, "rv32i_smcdeleg1p0"
# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"

Expand Down
2 changes: 2 additions & 0 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1027,6 +1027,7 @@ R"(All available -march extensions for RISC-V
smaia 1.0
smcdeleg 1.0
smcsrind 1.0
smdbltrp 1.0
smepmp 1.0
smmpm 1.0
smnpm 1.0
Expand All @@ -1038,6 +1039,7 @@ R"(All available -march extensions for RISC-V
sscofpmf 1.0
sscounterenw 1.0
sscsrind 1.0
ssdbltrp 1.0
ssnpm 1.0
sspm 1.0
ssqosid 1.0
Expand Down