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[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)
Smdbltrp and Ssdbltrp supports are added in this PR. Specification link(Smdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url) Specification link(Ssdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -120,6 +120,7 @@
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// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
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// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
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// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
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// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
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// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
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// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
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// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
@@ -131,6 +132,7 @@
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// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
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// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
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// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
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// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level)
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// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
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// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
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// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)

‎clang/test/Preprocessor/riscv-target-features.c

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// CHECK-NOT: __riscv_smaia {{.*$}}
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// CHECK-NOT: __riscv_smcdeleg {{.*$}}
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// CHECK-NOT: __riscv_smcsrind {{.*$}}
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// CHECK-NOT: __riscv_smdbltrp {{.*$}}
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// CHECK-NOT: __riscv_smepmp {{.*$}}
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// CHECK-NOT: __riscv_smrnmi {{.*$}}
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// CHECK-NOT: __riscv_smstateen {{.*$}}
@@ -39,6 +40,7 @@
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// CHECK-NOT: __riscv_sscofpmf {{.*$}}
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// CHECK-NOT: __riscv_sscounterenw {{.*$}}
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// CHECK-NOT: __riscv_sscsrind {{.*$}}
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// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
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// CHECK-NOT: __riscv_ssqosid{{.*$}}
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// CHECK-NOT: __riscv_ssstateen {{.*$}}
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// CHECK-NOT: __riscv_ssstrict {{.*$}}
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
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// CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismdbltrp1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64ismdbltrp1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
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// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32issdbltrp1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64issdbltrp1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
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// CHECK-SSDBLTRP-EXT: __riscv_ssdbltrp 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -129,6 +129,7 @@ on support follow.
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``Smaia`` Supported
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``Smcdeleg`` Supported
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``Smcsrind`` Supported
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``Smdbltrp`` Supported
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``Smepmp`` Supported
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``Smmpm`` Supported
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``Smnpm`` Supported
@@ -140,6 +141,7 @@ on support follow.
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``Sscofpmf`` Assembly Support
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``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Sscsrind`` Supported
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``Ssdbltrp`` Supported
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``Ssnpm`` Supported
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``Sspm`` Supported
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``Ssqosid`` Assembly Support

‎llvm/docs/ReleaseNotes.md

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@@ -186,6 +186,7 @@ Changes to the RISC-V Backend
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* Added `Smctr`, `Ssctr` and `Svvptc` extensions.
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* `-mcpu=syntacore-scr7` was added.
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* The `Zacas` extension is no longer marked as experimental.
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* Added Smdbltrp, Ssdbltrp extensions to -march.
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* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
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are no longer marked as experimental.
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* The `Sha` extension is now supported.

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -936,6 +936,13 @@ def FeatureStdExtSscsrind
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: RISCVExtension<"sscsrind", 1, 0,
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"'Sscsrind' (Indirect CSR Access Supervisor Level)">;
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def FeatureStdExtSmdbltrp
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: RISCVExtension<"smdbltrp", 1, 0,
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"'Smdbltrp' (Double Trap Machine Level)">;
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def FeatureStdExtSsdbltrp
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: RISCVExtension<"ssdbltrp", 1, 0,
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"'Ssdbltrp' (Double Trap Supervisor Level)">;
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def FeatureStdExtSmepmp
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: RISCVExtension<"smepmp", 1, 0,
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"'Smepmp' (Enhanced Physical Memory Protection)">;

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -117,6 +117,8 @@
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; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
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; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
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; RUN: llc -mtriple=riscv32 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMDBLTRP %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
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; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
@@ -263,6 +265,8 @@
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; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
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; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
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; RUN: llc -mtriple=riscv64 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMDBLTRP %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
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; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
@@ -415,6 +419,8 @@
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; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
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; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
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; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
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; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
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; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
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; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
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; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
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; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
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; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
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; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
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; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
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; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
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; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
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; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
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; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
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; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32i_sscsrind1p0"
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# CHECK: attribute 5, "rv32i2p1_sscsrind1p0"
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.attribute arch, "rv32i_smdbltrp1p0"
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# CHECK: attribute 5, "rv32i2p1_smdbltrp1p0"
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.attribute arch, "rv32i_ssdbltrp1p0"
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# CHECK: attribute 5, "rv32i2p1_ssdbltrp1p0"
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.attribute arch, "rv32i_smcdeleg1p0"
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# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
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‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1027,6 +1027,7 @@ R"(All available -march extensions for RISC-V
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smaia 1.0
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smcdeleg 1.0
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smcsrind 1.0
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smdbltrp 1.0
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smepmp 1.0
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smmpm 1.0
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smnpm 1.0
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sscofpmf 1.0
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sscounterenw 1.0
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sscsrind 1.0
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ssdbltrp 1.0
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ssnpm 1.0
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sspm 1.0
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ssqosid 1.0

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