LLVM and SPIRV-LLVM-Translator pulldown (WW16 2024) #13484
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Now readNext defaults to unaligned accesses. This patch drops unaligned to improve readability.
…arge (#88172) Following #78348, we should treat functions with an explicit section as small, unless the section name is (or has the prefix) ".ltext". Clang emits global initializers into a ".text.startup" section on Linux. If we mix small/medium code model object files with large code model object files, we'll end up mixing sections with and without the large section flag. Reland of #87838 with a check for non-ELF platforms in TargetMachine::isLargeGlobalValue(), otherwise MCJIT on Windows tests fail.
The test shows that name preservation doesn't work properly when --include-generated-funcs is used.
This test is meant to demonstrate an upcoming change that replaces basic block labels by FileCheck patterns.
Add the fir.cuda_deallocate operation that perform device deallocation of data hold by a descriptor. This will replace the call to AllocatableDeallocate from the runtime. This is a companion operation to the one added in #88586
CONFLICT (content): Merge conflict in clang/lib/CodeGen/CGExprCXX.cpp
VPBlendRecipes don't get lowered to phis and usually do not appear at the beginning of blocks, due to their masks appearing before them. This effectively relaxes an over-eager verifier message. Fixes llvm/llvm-project#88297. Fixes llvm/llvm-project#88804.
This is essentially the same as #82404 but has the `nneg` flag which allows the backend to reliably undo the transform. Closes #88299
This vendor extension has the same shift_add as zba, and most of the same patterns are duplicated. Enable it here too so the configurations don't diverge.
This reverts commit c6e38b9. Causes miscompiles, see comments on #78304.
…educe.{fmin,fmax,fmaximum,fminimum}`; NFC
…ce.{fmin,fmax,fmaximum,fminimum}`
Closes #88408
Fix a use of inline code markup to have a non-word character after the ending delimiter as required by reST.
libc.incude.fenv -> libc.include.fenv
…iles (#88994) followed the same style used in "TensorOps.td".
CONFLICT (content): Merge conflict in libclc/CMakeLists.txt
…e backend. (#88954) This is largely a revert of commit e817966. As #88029 shows, there exists hardware that only supports unaligned scalar. I'm leaving how this gets exposed to the clang interface to a future patch.
The previous patch was reverted because the test fails to build when libsanitizers is not present. This patch catches the BuildError exception and skips the test appropriately. This patch tests LLDB integration with libsanitizers for ASan. rdar://111856681
- With the memory operand as the destination, 'mr' variants of CFCMOV works like STORE and their memory operands should be input operands instead of output ones. Reviewers: XinWang10, arsenm Pull Request: llvm/llvm-project#88970
This change updates a few of the transformations in foldFMulReassoc to respect absent fast-math flags in cases where fmul and fdiv, fadd, or fsub instructions were being folded but the code was only checking for fast-math flags on the fmul instruction and was transferring flags to the folded instruction that were not present on the other original instructions. This fixes llvm/llvm-project#82857
…… (#88249) …se of tensor pack When the vector sizes are not passed as inputs to the vector transform operation, the vector sizes are queried from the static result shape in the case of tensor.pack op.
Since 97fe519, in ARM64EC mode, we don't define `__aarch64__`. Fix various preprocessor guards to account for this.
This reverts commit 7d4e8c1. Contrary to the commit description, this does cause large compile-time regressions (up to 10% on individual files).
- Those special register stores are STORE and their memory operands are input operands instead of output ones. Reviewers: JDevlieghere, arsenm, yinying-lisa-li, koachan, PeimingLiu, jyknight, aartbik, matthias-springer Reviewed By: arsenm Pull Request: llvm/llvm-project#88971
- If a def operand includes multiple sub-operands, count them when generating instr info. - Found issues in x86 and sparc backends, where memory operands of store or store-like instructions are wrongly placed in the output list. Reviewers: jayfoad, arsenm, Pierre-vh Reviewed By: arsenm Pull Request: llvm/llvm-project#88972
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@intel/dpcpp-cfe-reviewers @intel/dpcpp-spirv-reviewers @vmaksimo Can you have a look and add comments/approval explicitly so that this can be merged. Thanks. |
vmaksimo
approved these changes
Apr 22, 2024
smanna12
approved these changes
Apr 22, 2024
…needed to authenticate signed pointers (#86923) To authenticate pointers, CodeGen needs access to the key and discriminators that were used to sign the pointer. That information is sometimes known from the context, but not always, which is why `Address` needs to hold that information. This patch adds methods and data members to `Address`, which will be needed in subsequent patches to authenticate signed pointers, and uses the newly added methods throughout CodeGen. Although this patch isn't strictly NFC as it causes CodeGen to use different code paths in some cases (e.g., `mergeAddressesInConditionalExpr`), it doesn't cause any changes in functionality as it doesn't add any information needed for authentication. In addition to the changes mentioned above, this patch introduces class `RawAddress`, which contains a pointer that we know is unsigned, and adds several new functions for creating `Address` and `LValue` objects. This reapplies d9a685a, which was reverted because it broke ubsan bots. There seems to be a bug in coroutine code-gen, which is causing EmitTypeCheck to use the wrong alignment. For now, pass alignment zero to EmitTypeCheck so that it can compute the correct alignment based on the passed type (see function EmitCXXMemberOrOperatorMemberCallExpr).
Fixes for sycl
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Incorporate #13358 into pulldown. |
Looks great. Thanks for making sure this is done right |
ldrumm
approved these changes
Apr 23, 2024
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@bader @intel/llvm-gatekeepers This is ready for merge now. Thanks. |
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@bader is on vacation. @intel/llvm-gatekeepers Can someone issue a |
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/merge |
bb-sycl
approved these changes
Apr 24, 2024
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Wed 24 Apr 2024 03:16:27 AM UTC --- Start to merge the commit into sycl branch. It will take several minutes. |
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Wed 24 Apr 2024 03:20:42 AM UTC --- Merge the branch in this PR to base automatically. Will close the PR later. |
Thank you @aelovikov-intel |
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LLVM: llvm/llvm-project@af7a82f
SPIRV-LLVM-Translator: KhronosGroup/SPIRV-LLVM-Translator@e1f7ebee5ed8b90