igzip/riscv64: Optimize isal_adler32_rvv with 4x loop unrolling and tail agnostic(ta) #373
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leiwen2025
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It looks like among the 3 commits, one is empty and the other two are the same. Can you merge them into one? |
leiwen2025
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Done. I have merged them as requested. |
| add a1, a1, t4 | ||
| sub a2, a2, t4 | ||
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| vsetvli zero, t1, e32, m4, tu, ma |
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Maybe it's better to use zero, zero here to represent processing the same number of elements as before? (including some other vset)
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I will make the modifications as suggested.
| vle8.v v2, (a4) | ||
| add a5, a4, t1 | ||
| vle8.v v3, (a5) | ||
| mv t5, a2 |
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Same as before unrolling, this can be moved outside the loop, as long as vrsub.vx usage is changed to a2, and the modification of a2 is moved to a bit later
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Thanks for the review. I will modify this part
| add a4, a3, t1 | ||
| vle8.v v2, (a4) | ||
| add a5, a4, t1 | ||
| vle8.v v3, (a5) |
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Here we can use the same register
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I will make the modifications as suggested.
| vmv.x.s a4, v0 // B = a4 | ||
| vmv.x.s t2, v24 // A = t2 | ||
| add t3, t4, t3 | ||
| add t3, a4, t3 |
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No need to change the name here
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I will make the modifications as suggested.
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How is it looking now, @sunyuechi ? |
| vid.v v12 // 0, 1, 2, .. vl-1 | ||
| vadd.vv v8, v8, v4 | ||
| vrsub.vx v12, v12, a2 // len, len-1, len-2 | ||
| vwmaccu.vv v16, v12, v4 // v16: B += weight * next |
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| sub a2, a2, t1 | ||
| bnez a2, single | ||
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| 3: |
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The numbering is 1: 3: 4: but missing 2:. It might be better to use
1: 2: 3: instead.
| vadd.vv v8, v8, v28 | ||
| vwmaccu.vv v16, v12, v28 | ||
| sub a2, a2, a4 | ||
| bge a2, t0, unroll_loop_4x |
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Please move the sub instruction earlier to avoid the dependency
with bge.
| vwmaccu.vv v16, v12, v4 // v16: B += weight * next | ||
| add a1, a1, t1 | ||
| bnez a2, 1b | ||
| sub a2, a2, t1 |
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Please move the sub instruction earlier to avoid the dependency
with bge.
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After addressing the above minor issues, |
Thanks for the review. I 'll address the issues and merge the commits. |
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…ail agnostic(ta) Signed-off-by: WenLei <[email protected]>
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LGTM |
3 participants
This PR optimizes adler32_rvv implementation by introducing 4x loop unrolling and tail agnostic(ta) policy.
The optimization has been verified on the SG2044 platform: