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bump CBMC dependency #890

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Merged
merged 1 commit into from
Dec 20, 2024
Merged

bump CBMC dependency #890

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1 change: 1 addition & 0 deletions CHANGELOG
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# EBMC 5.5

* Verilog: bugfix for $onehot0
* Verilog: fix for primitive gates with more than two inputs

# EBMC 5.4
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2 changes: 1 addition & 1 deletion lib/cbmc
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Submodule cbmc updated 3 files
+5 −10 src/solvers/flattening/boolbv_onehot.cpp
+1 −0 unit/Makefile
+92 −0 unit/solvers/flattening/boolbv_onehot.cpp
4 changes: 2 additions & 2 deletions regression/verilog/SVA/system_verilog_assertion3.desc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
CORE broken-smt-backend
CORE
system_verilog_assertion3.sv
--module main --bound 1
--module main --bound 0
^EXIT=0$
^SIGNAL=0$
--
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7 changes: 4 additions & 3 deletions regression/verilog/SVA/system_verilog_assertion3.sv
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Expand Up @@ -3,8 +3,9 @@ module main();
assert final ($onehot('b0001000));
assert final (!$onehot('b0101000));
assert final (!$onehot('b00000));
assert final ($onehot0('b00000));
assert final ($onehot0('b000100));
assert final (!$onehot0('b010100));
assert final (!$onehot0(6'b00000));
assert final (!$onehot0(6'b000100));
assert final (!$onehot0(6'b010100));
assert final ($onehot0(6'b111101));

endmodule
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