Verilog: allow whitespace between macro and arguments #447
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Verilog allows whitespace between the macro identifier and the parentheses when using a macro with parameters. Verilog disallows whitespace between the macro identifier and the parentheses when defining a macro with parameters. When whitespace is present, the macro is interpreted as a macro without parameters.
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| // Is there a parameter list? | ||
| // These have been introduced in Verilog 2001. | ||
| // 1800-2017: "The left parenthesis shall follow the text macro name | ||
| // immediately, with no space in between." |
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Just curious: does this mean that tools don't actually observe this? I'm a bit confused as the PR suggests the opposite of what the standard says is now being supported.
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The commit message gives more detail. There are two separate cases, and both were broken, and are fixed here simultaneously.
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When using a macro with parameters, Verilog does allow whitespace between the macro identifier and the parentheses. The implementation did not allow this before this PR.
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When defining a macro with parameters, Verilog disallows whitespace between the macro identifier and the
parentheses. The implementation did allow this, which resulted in wrongly interpreted macro definitions.
Verilog allows whitespace between the macro identifier and the parentheses.