Verilog: allow whitespace between macro and arguments

Verilog allows whitespace between the macro identifier and the parentheses.

Author: kroening

regression/verilog/preprocessor/define1.desc

@@ -13,6 +13,7 @@ value
 
 x-y-z
 x-y-value
+moo-foo-bar
 ^EXIT=0$
 ^SIGNAL=0$
 --

regression/verilog/preprocessor/define1.v

@@ -7,3 +7,4 @@
 `define with_parameter(a, b, c) a-b-c
 `with_parameter(x, y, z)
 `with_parameter(x, y, `with_value)
+`with_parameter (moo, foo, bar)

src/verilog/verilog_preprocessor.cpp

@@ -277,6 +277,9 @@ auto verilog_preprocessort::parse_define_arguments(const definet &define)
   if(define.parameters.empty())
     return {};
 
+  // skip whitespace
+  tokenizer().skip_ws();
+
   if(tokenizer().next_token() != '(')
     throw verilog_preprocessor_errort() << "expecting define arguments";