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relax bitvector constant check for Verilog bitvectors #8191

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Merged
merged 1 commit into from
Feb 6, 2024

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@kroening kroening commented Feb 6, 2024

Verilog bitvectors use a four-valued logic, and hence do not meet the requirements of their binary counterparts.

  • Each commit message has a non-empty body, explaining why the change was made.
  • Methods or procedures I have added are documented, following the guidelines provided in CODING_STANDARD.md.
  • The feature or user visible behaviour I have added or modified has been documented in the User Guide in doc/cprover-manual/
  • Regression or unit tests are included, or existing tests cover the modified code (in this case I have detailed which ones those are in the commit message).
  • My commit message includes data points confirming performance improvements (if claimed).
  • My PR is restricted to a single feature or bugfix.
  • White-space or formatting changes outside the feature-related changed lines are in commits of their own.

Verilog bitvectors use a four-valued logic, and hence do not meet the
requirements of their binary counterparts.
@kroening kroening marked this pull request as ready for review February 6, 2024 13:09
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codecov bot commented Feb 6, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Comparison is base (2d96b83) 79.68% compared to head (85bd173) 79.68%.
Report is 2 commits behind head on develop.

Additional details and impacted files
@@           Coverage Diff            @@
##           develop    #8191   +/-   ##
========================================
  Coverage    79.68%   79.68%           
========================================
  Files         1681     1681           
  Lines       195296   195296           
========================================
  Hits        155624   155624           
  Misses       39672    39672           

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@kroening kroening enabled auto-merge February 6, 2024 14:41
@kroening kroening merged commit 40a981f into develop Feb 6, 2024
@tautschnig tautschnig deleted the bitvector-constant-verilogbv branch February 6, 2024 15:30
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2 participants