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Merge pull request #8191 from diffblue/bitvector-constant-verilogbv
relax bitvector constant check for Verilog bitvectors
2 parents d333f3b + 85bd173 commit 40a981f

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src/util/std_expr.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,17 @@ void constant_exprt::check(const exprt &expr, const validation_modet vm)
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vm,
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!can_cast_type<bitvector_typet>(expr.type()) ||
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can_cast_type<pointer_typet>(expr.type()) ||
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expr.type().id() == ID_verilog_unsignedbv ||
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expr.type().id() == ID_verilog_signedbv ||
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id2string(value).find_first_not_of("0123456789ABCDEF") ==
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std::string::npos,
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"negative bitvector constant must use two's complement");
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DATA_CHECK(
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vm,
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!can_cast_type<bitvector_typet>(expr.type()) || value == ID_0 ||
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!can_cast_type<bitvector_typet>(expr.type()) ||
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expr.type().id() == ID_verilog_unsignedbv ||
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expr.type().id() == ID_verilog_signedbv || value == ID_0 ||
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id2string(value)[0] != '0',
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"bitvector constant must not have leading zeros");
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}

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