musca_a1_wip

arch/arm/CMakeLists.txt

@@ -6,6 +6,7 @@ set(ARCH_FOR_cortex-m3     armv7-m     )
 set(ARCH_FOR_cortex-m4     armv7e-m    )
 set(ARCH_FOR_cortex-m23    armv8-m.base)
 set(ARCH_FOR_cortex-m33    armv8-m.main)
+zephyr_cc_option(-mcmse)
 
 set_property(GLOBAL PROPERTY E_KERNEL_ENTRY  -e${CONFIG_KERNEL_ENTRY})
 
@@ -14,6 +15,7 @@ if(${ARCH_FOR_${GCC_M_CPU}})
 endif()
 
 zephyr_compile_options(
+  -mcmse
   -mabi=aapcs
   ${TOOLCHAIN_C_FLAGS}
   ${ARCH_FLAG}

arch/arm/core/swap_helper.S

@@ -249,7 +249,6 @@ _stack_frame_endif:
     * Planned implementation of system calls for memory protection will
     * expand this case.
     */
-
     cmp r1, #2
     beq _oops
 
@@ -299,6 +298,13 @@ SECTION_FUNC(TEXT, __svc)
     * expand this case.
     */
     ands r1, #0xff
+
+    cmp r1, #10
+    beq _do_tfm_core_call
+
+    cmp r1, #11
+    beq _do_tfm_multiple_call
+
 #if CONFIG_USERSPACE
     mrs r2, CONTROL
 
@@ -351,6 +357,55 @@ _oops:
     blx _do_kernel_oops
     pop {pc}
 
+_do_tfm_core_call:
+    push {r0, lr}
+    ldr ip, [r0, #0]
+    ldr r0, [r0, #4]
+    ldr r1, [r0, #4]
+    ldr r2, [r0, #8]
+    ldr r3, [r0, #12]
+    ldr r0, [r0]
+    blx ip
+    pop {r1, lr}
+    str r0, [r1]
+    bx lr
+
+_do_tfm_multiple_call:
+    push {r0, lr}
+    ldr ip, [r0, #0]
+    ldr r0, [r0, #4]
+    ldr r1, [r0, #4]
+    ldr r2, [r0, #8]
+    ldr r3, [r0, #12]
+    ldr r0, [r0]
+    blx ip
+    pop {r1, lr}
+    cmp r0, #0
+    bne failed_first_call
+
+    # second call
+    push {r1, lr}
+    mov r0, r1
+    ldr ip, [r0, #0]
+    ldr r0, [r0, #4]
+    ldr r1, [r0, #4]
+    ldr r2, [r0, #8]
+    ldr r3, [r0, #12]
+    ldr r0, [r0]
+    blx ip
+    pop {r1, lr}
+    cmp r0, #0
+    beq ret_call
+    ldr r0, =#27
+    b ret_call
+    # first call fails, CORE_TEST_ERRNO_SECOND_CALL_FAILED
+
+failed_first_call:
+    ldr r0, =#26
+ret_call:
+    str r0, [r1]
+    bx lr
+
 #if CONFIG_USERSPACE
     /*
      * System call will setup a jump to the _do_arm_syscall function
@@ -390,7 +445,6 @@ valid_syscall_id:
     /* return from SVC to the modified LR - _arm_do_syscall */
     bx lr
 #endif
-
 #else
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

arch/arm/soc/arm/mps2/Kconfig.defconfig.mps2_an521

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2018 Arm Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_MPS2_AN521
+
+config SOC
+	default mps2_an521
+
+config NUM_IRQS
+	int
+	default 96
+
+endif

arch/arm/soc/arm/mps2/Kconfig.soc

@@ -12,4 +12,8 @@ config SOC_MPS2_AN385
 	bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)"
 	select CPU_CORTEX_M3
 
+config SOC_MPS2_AN521
+	bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521)"
+	select CPU_CORTEX_M33
+
 endchoice

arch/arm/soc/arm/mps2/soc.h

@@ -7,6 +7,12 @@
 #ifndef _SOC_H_
 #define _SOC_H_
 
+#if defined(CONFIG_SOC_MPS2_AN521)
+#define __SAUREGION_PRESENT       1U        /* SAU regions present */
+#define __FPU_PRESENT             CONFIG_CPU_HAS_FPU
+#define __DSP_PRESENT             1U        /* no DSP extension present */
+#endif
+
 #include <soc_devices.h>
 
 #endif /* _SOC_H_ */

boards/arm/mps2_an521/CMakeLists.txt

@@ -0,0 +1,3 @@
+zephyr_library()
+zephyr_library_sources(pinmux.c)
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)

boards/arm/mps2_an521/Kconfig.board

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_MPS2_AN521
+	bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521)"
+	depends on SOC_SERIES_MPS2

boards/arm/mps2_an521/Kconfig.defconfig

@@ -0,0 +1,127 @@
+#
+# Copyright (c) 2018 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MPS2_AN521
+
+config BOARD
+	default mps2_an521
+
+if GPIO
+
+config GPIO_CMSDK_AHB
+	def_bool y
+
+config GPIO_CMSDK_AHB_PORT0
+	def_bool y
+
+config GPIO_CMSDK_AHB_PORT1
+	def_bool y
+
+config GPIO_CMSDK_AHB_PORT2
+	def_bool y
+
+config GPIO_CMSDK_AHB_PORT3
+	def_bool y
+
+endif # GPIO
+
+if PINMUX
+
+config PINMUX_MPS2
+	def_bool y
+
+endif # PINMUX
+
+if SERIAL
+
+config UART_CMSDK_APB
+	def_bool y
+
+config UART_INTERRUPT_DRIVEN
+	def_bool y
+
+config UART_CMSDK_APB_PORT0
+	def_bool y
+
+config UART_CMSDK_APB_PORT1
+	def_bool y
+
+config UART_CMSDK_APB_PORT2
+	def_bool y
+
+config UART_CMSDK_APB_PORT3
+	def_bool y
+
+config UART_CMSDK_APB_PORT4
+	def_bool y
+
+endif # SERIAL
+
+if WATCHDOG
+
+config WDOG_CMSDK_APB
+	def_bool y
+
+endif # WATCHDOG
+
+if COUNTER
+
+if COUNTER_TMR_CMSDK_APB
+
+config COUNTER_TMR_CMSDK_APB_0
+	def_bool y
+
+config COUNTER_TMR_CMSDK_APB_1
+	def_bool y
+
+endif # COUNTER_TMR_CMSDK_APB
+
+if TIMER_TMR_CMSDK_APB
+
+config TIMER_TMR_CMSDK_APB_0
+	def_bool y
+
+config TIMER_TMR_CMSDK_APB_1
+	def_bool y
+
+endif # TIMER_TMR_CMSDK_APB
+
+if COUNTER_DTMR_CMSDK_APB
+
+config COUNTER_DTMR_CMSDK_APB_0
+	def_bool y
+
+endif # COUNTER_DTMR_CMSDK_APB
+
+if TIMER_DTMR_CMSDK_APB
+
+config TIMER_DTMR_CMSDK_APB_0
+	def_bool y
+
+endif # TIMER_DTMR_CMSDK_APB
+
+endif # COUNTER
+
+if I2C
+
+config I2C_SBCON
+	def_bool y
+
+config I2C_SBCON_0
+	def_bool y
+
+config I2C_SBCON_1
+	def_bool y
+
+config I2C_SBCON_2
+	def_bool y
+
+config I2C_SBCON_3
+	def_bool y
+
+endif # I2C
+
+endif

boards/arm/mps2_an521/board.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#if defined(CONFIG_GPIO_MMIO32)
+
+/* USERLED0 */
+#define LED0_GPIO_PORT	FPGAIO_LED0_GPIO_NAME
+#define LED0_GPIO_PIN	FPGAIO_LED0_USERLED0
+
+/* USERLED1 */
+#define LED1_GPIO_PORT	FPGAIO_LED0_GPIO_NAME
+#define LED1_GPIO_PIN	FPGAIO_LED0_USERLED1
+
+/* USERPB0 */
+#define SW0_GPIO_NAME	FPGAIO_BUTTON_GPIO_NAME
+#define SW0_GPIO_PIN	FPGAIO_BUTTON_USERPB0
+
+/* USERPB1 */
+#define SW1_GPIO_NAME	FPGAIO_BUTTON_GPIO_NAME
+#define SW1_GPIO_PIN	FPGAIO_BUTTON_USERPB1
+
+#endif /* CONFIG_GPIO_MMIO32 */
+
+#endif /* __INC_BOARD_H */

boards/arm/mps2_an521/dts.fixup

@@ -0,0 +1,81 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+/* CMSDK APB Timers */
+#define CMSDK_APB_TIMER0			ARM_CMSDK_TIMER_40000000_BASE_ADDRESS_0
+#define CMSDK_APB_TIMER_0_IRQ			ARM_CMSDK_TIMER_40000000_IRQ_0
+
+#define CMSDK_APB_TIMER1			ARM_CMSDK_TIMER_40001000_BASE_ADDRESS_0
+#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1	ARM_CMSDK_TIMER_40001000_IRQ_0
+
+/* CMSDK APB Dual Timer */
+#define CMSDK_APB_DTIMER			ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS_0
+#define CMSDK_APB_DUALTIMER_IRQ			ARM_CMSDK_DTIMER_40002000_IRQ_0
+
+/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
+#define CMSDK_APB_UART0				ARM_CMSDK_UART_40200000_BASE_ADDRESS_0
+#define CMSDK_APB_UART_0_IRQ_TX			ARM_CMSDK_UART_40200000_IRQ_0
+#define CMSDK_APB_UART_0_IRQ_RX			ARM_CMSDK_UART_40200000_IRQ_1
+#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI	ARM_CMSDK_UART_40200000_IRQ_0_PRIORITY
+#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE	ARM_CMSDK_UART_40200000_CURRENT_SPEED
+#define CONFIG_UART_CMSDK_APB_PORT0_NAME	ARM_CMSDK_UART_40200000_LABEL
+
+#define CMSDK_APB_UART1				ARM_CMSDK_UART_40201000_BASE_ADDRESS_0
+#define CMSDK_APB_UART_1_IRQ_TX			ARM_CMSDK_UART_40201000_IRQ_0
+#define CMSDK_APB_UART_1_IRQ_RX			ARM_CMSDK_UART_40201000_IRQ_1
+#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI	ARM_CMSDK_UART_40201000_IRQ_0_PRIORITY
+#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE	ARM_CMSDK_UART_40201000_CURRENT_SPEED
+#define CONFIG_UART_CMSDK_APB_PORT1_NAME	ARM_CMSDK_UART_40201000_LABEL
+
+#define CMSDK_APB_UART2				ARM_CMSDK_UART_40202000_BASE_ADDRESS_0
+#define CMSDK_APB_UART_2_IRQ_TX			ARM_CMSDK_UART_40202000_IRQ_0
+#define CMSDK_APB_UART_2_IRQ_RX			ARM_CMSDK_UART_40202000_IRQ_1
+#define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI	ARM_CMSDK_UART_40202000_IRQ_0_PRIORITY
+#define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE	ARM_CMSDK_UART_40202000_CURRENT_SPEED
+#define CONFIG_UART_CMSDK_APB_PORT2_NAME	ARM_CMSDK_UART_40202000_LABEL
+
+#define CMSDK_APB_UART3				ARM_CMSDK_UART_40203000_BASE_ADDRESS_0
+#define CMSDK_APB_UART_3_IRQ_TX			ARM_CMSDK_UART_40203000_IRQ_0
+#define CMSDK_APB_UART_3_IRQ_RX			ARM_CMSDK_UART_40203000_IRQ_1
+#define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI	ARM_CMSDK_UART_40203000_IRQ_0_PRIORITY
+#define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE	ARM_CMSDK_UART_40203000_CURRENT_SPEED
+#define CONFIG_UART_CMSDK_APB_PORT3_NAME	ARM_CMSDK_UART_40203000_LABEL
+
+#define CMSDK_APB_UART4				ARM_CMSDK_UART_40204000_BASE_ADDRESS_0
+#define CMSDK_APB_UART_4_IRQ_TX			ARM_CMSDK_UART_40204000_IRQ_0
+#define CMSDK_APB_UART_4_IRQ_RX			ARM_CMSDK_UART_40204000_IRQ_1
+#define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI	ARM_CMSDK_UART_40204000_IRQ_0_PRIORITY
+#define CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE	ARM_CMSDK_UART_40204000_CURRENT_SPEED
+#define CONFIG_UART_CMSDK_APB_PORT4_NAME	ARM_CMSDK_UART_40204000_LABEL
+
+/* CMSDK APB Watchdog */
+#define CMSDK_APB_WDOG				ARM_CMSDK_WATCHDOG_40081000_BASE_ADDRESS_0
+
+/* CMSDK AHB General Purpose Input/Output (GPIO) */
+#define CMSDK_AHB_GPIO0				ARM_CMSDK_GPIO_40100000_BASE_ADDRESS_0
+#define IRQ_PORT0_ALL				ARM_CMSDK_GPIO_40100000_IRQ_0
+
+#define CMSDK_AHB_GPIO1				ARM_CMSDK_GPIO_40101000_BASE_ADDRESS_0
+#define IRQ_PORT1_ALL				ARM_CMSDK_GPIO_40101000_IRQ_0
+
+#define CMSDK_AHB_GPIO2				ARM_CMSDK_GPIO_40102000_BASE_ADDRESS_0
+#define IRQ_PORT2_ALL				ARM_CMSDK_GPIO_40102000_IRQ_0
+
+#define CMSDK_AHB_GPIO3				ARM_CMSDK_GPIO_40103000_BASE_ADDRESS_0
+#define IRQ_PORT3_ALL				ARM_CMSDK_GPIO_40103000_IRQ_0
+
+/* I2C SBCon */
+#define I2C_SBCON_0_BASE_ADDR			ARM_VERSATILE_I2C_50207000_BASE_ADDRESS_0
+#define I2C_SBCON_0_NAME			ARM_VERSATILE_I2C_50207000_LABEL
+
+#define I2C_SBCON_1_BASE_ADDR			ARM_VERSATILE_I2C_50208000_BASE_ADDRESS_0
+#define I2C_SBCON_1_NAME			ARM_VERSATILE_I2C_50208000_LABEL
+
+#define I2C_SBCON_2_BASE_ADDR			ARM_VERSATILE_I2C_5020C000_BASE_ADDRESS_0
+#define I2C_SBCON_2_NAME			ARM_VERSATILE_I2C_5020C000_LABEL
+
+#define I2C_SBCON_3_BASE_ADDR			ARM_VERSATILE_I2C_5020D000_BASE_ADDRESS_0
+#define I2C_SBCON_3_NAME			ARM_VERSATILE_I2C_5020D000_LABEL
+
+/* End of SoC Level DTS fixup file */