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verilog-to-routing / vtr-verilog-to-routing Public

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Stratix 10 Quad Port Ram Support#3180

Merged

AlexandreSinger merged 6 commits intomasterverilog-to-routing/vtr-verilog-to-routing:masterfrom

stratix_10_arch_updatesverilog-to-routing/vtr-verilog-to-routing:stratix_10_arch_updatesCopy head branch name to clipboard

Sep 19, 2025

Conversation Commits6 (6)Checks Files changed

Merged

Stratix 10 Quad Port Ram Support#3180
AlexandreSinger merged 6 commits intomasterfrom
stratix_10_arch_updates

Commits

Commits on Sep 1, 2025

Add memory class attribute to the mlab primitive in stratix 10 architecture
kimiatkh
committed
Add support for quad port rams
kimiatkh
committed
Add support for Stratix 10 quad port ram to vqm2blif
kimiatkh
committed
Add comments to S10 arch file for quad port rams
kimiatkh
committed
support escaped identifiers starting with ~ in vqm2blif
kimiatkh
committed

Commits on Sep 19, 2025

Merge branch 'master' into stratix_10_arch_updates
AlexandreSinger
authored

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