systemverilog

Here are 25 public repositories matching this topic...

pulp-platform / carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

c asic fpga simulation riscv systemverilog safety-critical heterogeneous-computing mixed-criticality-systems

Updated Jul 21, 2025
Tcl

Choaib-ELMADI / fpga-programming-for-beginners

Sponsor

Star

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

embedded fpga electronics vhdl embedded-systems verilog systemverilog fpga-soc fpga-board fpga-programming

Updated Aug 25, 2024
Tcl

icglue / icglue

Star

A Tcl-Library for scripted HDL generation

verilog systemverilog hdl verilog-hdl systemverilog-hdl tcl-applications

Updated Apr 30, 2024
Tcl

Enanter / ADPLL

Star

All Digital Phase-Locked Loop

systemverilog pll

Updated May 22, 2023
Tcl

MatthieuMichon / fpga-jtag-axi-demo

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Basic JTAG / AXI demonstration on Xilinx's FPGA.

fpga tcl xilinx vivado systemverilog jtag axi

Updated Apr 22, 2021
Tcl

timothystotts / fpga-serial-mem-tester-3

Star

A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.

fpga vhdl systemverilog pmod zybo-z7 arty-s7 arty-a7 systemonchip

Updated Aug 10, 2024
Tcl

Unicamp-Odhin / I2S_Microphone

Star

I2S Microphone peripheral written in SystemVerilog HDL

audio fpga verilog systemverilog audio-processing i2s i2s-microphone

Updated Jul 18, 2025
Tcl

timothystotts / fpga-serial-acl-tester-3

Star

A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.

fpga vhdl verilog systemverilog pmod zybo-z7 arty-s7 arty-a7 systemonchip

Updated Aug 10, 2024
Tcl

Unicamp-Odhin / PDM_Microphone

Star

PDM Microphone peripheral written in SystemVerilog HDL

audio verilog systemverilog audio-processing pdm

Updated May 19, 2025
Tcl

Unicamp-Odhin / FPGA_VGA_Workshop

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Este projeto tem como objetivo principal o desenvolvimento de um controlador VGA utilizando FPGA (Field-Programmable Gate Array) e linguagem de descrição de hardware (HDL).

fpga rtl systemverilog vga vga-controller

Updated Aug 8, 2025
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Unicamp-Odhin / FPGA_101

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Starting in the world of FPGAs!!!!!

fpga hardware verilog systemverilog fpga-programming

Updated Aug 8, 2025
Tcl

pawel2000pl / VerilogLedDriver

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Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller verilog vivado systemverilog pwm pwm-driver led-driver

Updated Jan 1, 2024
Tcl

Unicamp-Odhin / SPI-Slave

Star

SPI Slave module written in SystemVerilog HDL

fpga verilog spi systemverilog verilog-hdl openhardware systemverilog-hdl spislave

Updated May 12, 2025
Tcl

TahirZia-1 / Digital-Clock-Verilog

Star

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.