Enforce zero register in floating point operation #48
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Passed 5 more tests in riscv-arch-test:
fclass_b1-01
fcvt.wu.s_b23-01
flt_b19-01
fmv.x.w_b1-01
fmv.x.w_b24-01
vestata
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to vestata/rv32emu
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this pull request
Jan 24, 2025
Enforce zero register in floating point operation
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Passed 5 more tests in riscv-arch-test:
fclass_b1-01
fcvt.wu.s_b23-01
flt_b19-01
fmv.x.w_b1-01
fmv.x.w_b24-01