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Merged
merged 2 commits into from
Sep 24, 2025
Merged

Talos MDSS change #179

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6cce520
FROMLIST: arm64: dts: qcom: Add display support for QCS615
Sep 3, 2025
457e274
FROMLIST: arm64: dts: qcom: Add display support for QCS615 RIDE board
Sep 3, 2025
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150 changes: 150 additions & 0 deletions arch/arm64/boot/dts/qcom/qcs615-ride.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,18 @@
};
};

dp-dsi0-connector {
compatible = "dp-connector";
label = "DSI0";
type = "mini";

port {
dp_dsi0_connector_in: endpoint {
remote-endpoint = <&dsi2dp_bridge_out>;
};
};
};

vreg_conn_1p8: regulator-conn-1p8 {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_1p8";
Expand All @@ -65,6 +77,64 @@
regulator-always-on;
};

vreg_12p0: regulator-vreg-12p0 {
compatible = "regulator-fixed";
regulator-name = "VREG_12P0";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};

vreg_1p0: regulator-vreg-1p0 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P0";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;

vin-supply = <&vreg_1p8>;
};

vreg_1p8: regulator-vreg-1p8 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;

vin-supply = <&vreg_5p0>;
};

vreg_3p0: regulator-vreg-3p0 {
compatible = "regulator-fixed";
regulator-name = "VREG_3P0";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;

vin-supply = <&vreg_12p0>;
};

vreg_5p0: regulator-vreg-5p0 {
compatible = "regulator-fixed";
regulator-name = "VREG_5P0";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;

vin-supply = <&vreg_12p0>;
};

wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";

Expand Down Expand Up @@ -288,6 +358,86 @@
};
};

&i2c2 {
clock-frequency = <400000>;
status = "okay";

io_expander: pinctrl@3e {
compatible = "semtech,sx1509q";
reg = <0x3e>;
interrupts-extended = <&tlmm 58 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
semtech,probe-reset;
};

i2c-mux@77 {
compatible = "nxp,pca9542";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;

i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;

bridge@58 {
compatible = "analogix,anx7625";
reg = <0x58>;
interrupts-extended = <&io_expander 0 IRQ_TYPE_EDGE_FALLING>;
enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&vreg_1p0>;
vdd18-supply = <&vreg_1p8>;
vdd33-supply = <&vreg_3p0>;

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;

dsi2dp_bridge_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};

port@1 {
reg = <1>;

dsi2dp_bridge_out: endpoint {
remote-endpoint = <&dp_dsi0_connector_in>;
};
};
};
};
};
};
};

&mdss {
status = "okay";
};

&mdss_dsi0 {
vdda-supply = <&vreg_l11a>;
status = "okay";
};

&mdss_dsi0_out {
remote-endpoint = <&dsi2dp_bridge_in>;
data-lanes = <0 1 2 3>;
};

&mdss_dsi0_phy {
vcca-supply = <&vreg_l5a>;
status = "okay";
};

&pcie {
perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
Expand Down
182 changes: 180 additions & 2 deletions arch/arm64/boot/dts/qcom/sm6150.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,qcs615-camcc.h>
#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
Expand Down Expand Up @@ -3657,14 +3658,191 @@
#power-domain-cells = <1>;
};

mdss: display-subsystem@ae00000 {
compatible = "qcom,sm6150-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
reg-names = "mdss";

interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"cpu-cfg";

power-domains = <&dispcc MDSS_CORE_GDSC>;

clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;

interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;

iommus = <&apps_smmu 0x800 0x0>;

#address-cells = <2>;
#size-cells = <2>;
ranges;

status = "disabled";

mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sm6150-dpu";
reg = <0x0 0x0ae01000 0x0 0x8f000>,
<0x0 0x0aeb0000 0x0 0x2008>;
reg-names = "mdp",
"vbif";

clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";

operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_CX>;

interrupts-extended = <&mdss 0>;

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;

dpu_intf0_out: endpoint {
};
};

port@1 {
reg = <1>;

dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};

mdp_opp_table: opp-table {
compatible = "operating-points-v2";

opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};

opp-256000000 {
opp-hz = /bits/ 64 <256000000>;
required-opps = <&rpmhpd_opp_svs>;
};

opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};

mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae94000 0x0 0x400>;
reg-names = "dsi_ctrl";

interrupts-extended = <&mdss 4>;

clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";

assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;

operating-points-v2 = <&dsi0_opp_table>;
power-domains = <&rpmhpd RPMHPD_CX>;

phys = <&mdss_dsi0_phy>;

#address-cells = <1>;
#size-cells = <0>;

status = "disabled";

dsi0_opp_table: opp-table {
compatible = "operating-points-v2";

opp-164000000 {
opp-hz = /bits/ 64 <164000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
};

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;

mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};

port@1 {
reg = <1>;

mdss_dsi0_out: endpoint {
};
};
};
};

mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,sm6150-dsi-phy-14nm";
reg = <0x0 0x0ae94400 0x0 0x100>,
<0x0 0x0ae94500 0x0 0x300>,
<0x0 0x0ae94800 0x0 0x124>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";

#clock-cells = <1>;
#phy-cells = <0>;

clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"ref";

status = "disabled";
};
};

dispcc: clock-controller@af00000 {
compatible = "qcom,qcs615-dispcc";
reg = <0 0x0af00000 0 0x20000>;

clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<0>,
<0>,
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<0>,
<0>,
<0>;
Expand Down