[ROCm] group_index_select_or_add_2d_kernel forward pass optimization #5078
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…ices for group_index_select_or_add_2d_kernel
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spcyppt
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Nov 4, 2025
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| // The wave size is forced to be 32 on ROCm devices in favor | ||
| // of granularity losses reduction. | ||
| constexpr int EMULATED_WARP_SIZE = 32; |
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Can we ensure that EMULATED_WARP_SIZE = kWarpSize for CUDA?
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updated this in the internal diff.
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Nov 4, 2025
…h#5078) Summary: This PR introduces optimization for `group_index_select_or_add_2d_kernel` (`USE_INDEX_SELECT==true`) kernel with primary focus on `float` type and relatively small embedding dimensions. 2 things are implemented: 1) Extracted the common variables out of the loop to omit unnecessary synchronizations on memory load (compiler won't do that automatically) 2) Switch to 32 threads logical wave sizes to reduce granularity losses. Differential Revision: D86135611 Pulled By: q10
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Bernard-Liu
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Nov 11, 2025
…h#5080) Summary: Pull Request resolved: pytorch#5080 X-link: https://github.com/facebookresearch/FBGEMM/pull/2087 This PR introduces optimization for `group_index_select_or_add_2d_kernel` (`USE_INDEX_SELECT==true`) kernel with primary focus on `float` type and relatively small embedding dimensions. 2 things are implemented: 1) Extracted the common variables out of the loop to omit unnecessary synchronizations on memory load (compiler won't do that automatically) 2) Switch to 32 threads logical wave sizes to reduce granularity losses. Pull Request resolved: pytorch#5078 Reviewed By: spcyppt, haoyuz Differential Revision: D86135611 Pulled By: q10 fbshipit-source-id: f4fb9966f5f5180c4dde2aed92ca726c260b7743
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This PR introduces optimization for
group_index_select_or_add_2d_kernel(USE_INDEX_SELECT==true) kernel with primary focus onfloattype and relatively small embedding dimensions. 2 things are implemented: