atomics/powerpc: Fix WMB instruction #3661
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* `lwsync` is a write memory barrier.
- `eieio` is really not meant for this type of operation.
* `lwsync` can also be used for the read memory barrier according to
my reading of the of the Power 8 ISA docs (v2.07)
- https://www-01.ibm.com/marketing/iwm/iwm/web/reg/download.do?source=swg-opower&S_PKG=dl&lang=en_US&cp=UTF-8
* References openpmix/openpmix#391
Signed-off-by: Joshua Hursey <[email protected]>
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For those interested ping me offline if you cannot access the link in the PR description. The link below might also be of help (though it doesn't have all the finer details): |
bwbarrett
approved these changes
Jun 6, 2017
bosilca
approved these changes
Jun 6, 2017
rhc54
approved these changes
Jun 6, 2017
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@hjelmn I forgot to flag you on this PR. Per our conversation, do you have any reservations about this change? It's what we discussed. There is some question about if there is a different, lighter mechanism for the |
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I think lwsync is light enough for the read barrier for our use case. |
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PR this to 2.0.x, 2.x, and 3.0.x. |
This was referenced Jun 7, 2017
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Thanks - the three PRs have been filed to the release branches. |
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lwsyncis a write memory barrier.eieiois really not meant for this type of operation.lwsynccan also be used for the read memory barrier according tomy reading of the of the Power 8 ISA docs (v2.07)
Signed-off-by: Joshua Hursey [email protected]