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deac1c6
[SYCL][ESIMD] Change logic for tests on simd default constructor (#852)
vasilytric Feb 22, 2022
d43bc4e
[SYCL][ESIMD] Decrease type coverage for core tests (#832)
vasilytric Feb 22, 2022
95fd782
[SYCL][ESIMD] Add test on logical not operator (#784)
vasilytric Feb 22, 2022
803958e
[ESIMD] Temporary disable flaky tests (#853)
Feb 24, 2022
88ee9d1
[SYCL] Add tests for atomics with various memory orders and scopes (#…
t4c1 Feb 24, 2022
e737b79
[SYCL][ESIMD] Add tests for simd broadcast constructor (#690)
vasilytric Feb 24, 2022
d6527a5
[SYCL][ESIMD] Add tests on simd increment and decrement operators (#827)
vasilytric Feb 24, 2022
dacacdf
[SYCL][ESIMD] Add checks that device has fp16/fp64 aspects (#839)
vasilytric Feb 24, 2022
08100b0
Disable failing tests to fix CI checks. (#868)
bader Feb 24, 2022
78c3d9b
[SYCL][ESIMD] Replace std::max_align_t with 16 for overaligned (#846)
vasilytric Feb 24, 2022
6e7b3ce
[SYCL][ESIMD] Add tests for dpas API (#866)
sndmitriev Feb 25, 2022
7bb39d1
[SYCL] Temporary disable of all_of.cpp due to timeout on jenkins job …
denis-kabanov Feb 25, 2022
5e8f630
[SYCL] Align tests with 22.05.22297 GPU RT (#871)
vladimirlaz Feb 25, 2022
6f29028
[SYCL] Enable level-zero-link-flags and fix kernel_bundle_api (#806)
HabKaffee Feb 28, 2022
fa80b79
[ESIMD] Add scalar argument test cases to esimd_math.cpp (#864)
kbobrovs Mar 1, 2022
ad27262
[SYCL] Test indirect access memory tracking in the L0 plugin (#532)
againull Mar 1, 2022
79d449f
[ESIMD] Enable aot_mixed.cpp (#848)
kbobrovs Mar 1, 2022
95a81ea
[ESIMD] Add ABR mask case to esimd_rgba_smoke (commented out due to a…
kbobrovs Mar 1, 2022
857b056
[SYCL] Rework of pi tracing test (#876)
IgorKharchikov Mar 2, 2022
7a1e72a
Fix bug and improve strength of simd_view_copy_move_assign.cpp. (#877)
kbobrovs Mar 3, 2022
c7b9604
[SYCL] Updating tests for SYCL2020 errc conformance (#857)
cperkinsintel Mar 3, 2022
85d5a7c
Disable failing tests to fix CI checks (#886)
Fznamznon Mar 3, 2022
e75a5a5
[SYCL][ESIMD][EMU] Correction : Number of threads - esimd_merge.cpp (…
dongkyunahn-intel Mar 3, 2022
26f31ec
[SYCL] Remove XFAIL to reflect updated Driver. (#819)
rdeodhar Mar 4, 2022
cf29cb4
[SYCL] Enable GroupAlgorithm/SYCL2020/all_of.cpp on Windows (#883)
dm-vodopyanov Mar 4, 2022
9f807d9
[SYCL][ESIMD] Remove negative value for converted reference data (#874)
vasilytric Mar 4, 2022
32fbf01
[SYCL][CUDA] Add unit test for local arguments alignment (#608)
npmiller Mar 4, 2022
05418ad
[SYCL][ESIMD] Make logs architecture more flexible (#838)
yuriykoch Mar 4, 2022
8a78fda
[SYCL][Matrix] add tests for fill and slicing for int8 type and pack…
dkhaldi Mar 5, 2022
3338378
[ESIMD] Enable testcases with variable scatter mask, after compiler f…
kbobrovs Mar 5, 2022
c5012d6
[SYCL] Change level_zero_queue_profiling.cpp (#863)
HabKaffee Mar 5, 2022
b838a72
[SYCL] XPASS static-buffer-dtor.cpp with compute-runtime bump (#896)
steffenlarsen Mar 7, 2022
7f0ae77
[SYCL][ESIMD][EMU] ESIMD test updates for esimd_emulator backend (#869)
dongkyunahn-intel Mar 7, 2022
3c06ec2
[ESIMD] Add smoke test for pack_mask/unpack_mask APIs. (#826)
kbobrovs Mar 8, 2022
05909cd
Disable esimd_pack_unpack_mask test on OpenCL (#902)
bader Mar 8, 2022
347d71b
Use full namespace - cl::sycl::property::... - to disambiguate with o…
sherry-yuan Mar 8, 2022
f763b7f
[SYCL] Reenable USM pooling tests after feature has been made default…
rdeodhar Mar 9, 2022
b2897f9
[SYCL][ESIMD] Move some ESIMD APIs outside of experimental namespace …
sndmitriev Mar 9, 2022
e8fa63d
[SYCL][ESIMD] Update ESIMD/regression/dgetrf.cpp after renaming repli…
sndmitriev Mar 10, 2022
a5f90c0
[SYCL] Speed up atomic_ref tests (#879)
vladimirlaz Mar 10, 2022
0f3052b
[SYCL] Temporarily disable flaky test (#907)
alexbatashev Mar 10, 2022
1aaa62e
Disable lldiv test for SYCL device library since it will lead (#915)
jinge90 Mar 11, 2022
6cfcd72
[NFC] Update CODEOWNERS (#916)
MrSidims Mar 11, 2022
ad174cf
[SYCL][ESIMD] Move rounding functions out of experimental namespace (…
sndmitriev Mar 11, 2022
e3ff348
[ESIMD] Size correction for array containing result values (#913)
dongkyunahn-intel Mar 11, 2022
9992b63
[SYCL][ESIMD] Add tests for SVM gather/scatter with 1,2,4 elements (#…
sndmitriev Mar 13, 2022
44ef815
[SYCL][ESIMD] Add test on simd converting constructor (#695)
vasilytric Mar 13, 2022
0eae0ff
[BFloat16] Fix verify_logic test (#911)
Nuullll Mar 13, 2022
d944065
[SYCL][CUDA] Added tests for atomic loads and stores for various orde…
t4c1 Mar 14, 2022
2ace807
[SYCL][ESIMD] Enhance enum logging support (#917)
yuriykoch Mar 15, 2022
1947aed
[SYCL][ESIMD][EMU] Removing 'XFAIL' markings for 'single_task' tests …
dongkyunahn-intel Mar 15, 2022
c4efcc7
Disable std::ldiv test for SYCL device. (#920)
jinge90 Mar 16, 2022
357b73e
[SYCL] Add checks for overridden compile and link options (#894)
maximdimakov Mar 16, 2022
b08cf3b
[SYCL][Matrix] add automatic VNNI transform test (#903)
dkhaldi Mar 16, 2022
e218d1f
[SYCL] Add test for queue.get_property<in_order> (#924)
denis-kabanov Mar 19, 2022
b8ee3a5
[SYCL][HIP] Expect failure of some tests that have 'has(aspect::atomi…
denis-kabanov Mar 21, 2022
7794b50
[SYCL][ESIMD] Add tests on simd select 1D functions (#875)
vasilytric Mar 22, 2022
e36c713
[SYCL][ESIMD] Add test on simd bitwise not operator (#850)
vasilytric Mar 22, 2022
afc48b2
[SYCL] Adds regression test for reduction resource leak (#624)
steffenlarsen Mar 22, 2022
b83d0e1
[SYCL] Disable reduction resource leak tests on Windows (#933)
steffenlarsen Mar 22, 2022
763da7e
[SYCL] Add compatibility_testing parameter (#918)
vladimirlaz Mar 22, 2022
52c107f
[ESIMD] Enable simd_view_copy_move_assign.cpp test on Windows (#936)
v-klochkov Mar 23, 2022
5508775
[ESIMD] Added a test verifying dpas called for bfloat16 (#927)
v-klochkov Mar 23, 2022
cae3c2e
[SYCL] Enable reduction tests with ZE_DEBUG set (#930)
bso-intel Mar 23, 2022
0349610
[SYCL] Add exclusive scan over group test (#932)
aobolensk Mar 23, 2022
051850a
[SYCL] reenable L0 Win Sampler tests (#922)
cperkinsintel Mar 23, 2022
0f885d5
[SYCL] Enable parallel indexers for AMD, after adding global offset (…
jchlanda Mar 23, 2022
caf5e24
Revert "[SYCL] Enable parallel indexers for AMD, after adding global …
vladimirlaz Mar 23, 2022
bc668f8
[SYCL] [L0] [PI] Corrections to tests to ensure desired batching beha…
rdeodhar Mar 23, 2022
b8c62d2
[ESIMD] Fix the complex-lib-lin checking compilation from static libr…
v-klochkov Mar 24, 2022
03a9bca
[SYCL] Disable test assert_in_simultaneous_kernels due to flaky failu…
KseniyaTikhomirova Mar 24, 2022
5d372c0
[SYCL] Enable ESIMD/Regression/dgetrf.cpp test (#942)
HabKaffee Mar 24, 2022
b63c248
[SYCL][ESIMD][EMU] tolerated mismatch rate in binary files comparison…
lsatanov Mar 24, 2022
0c98489
[SYCL][ESIMD][EMU] Removing XFAIL for test enabled with memory intrin…
dongkyunahn-intel Mar 24, 2022
9660970
[SYCL][ESIMD] Move round_up_int_division function into functional/com…
vasilytric Mar 24, 2022
a3592f9
[SYCL][ESIMD][EMU] Removing XFAIL for mandelbrot.cpp (#947)
dongkyunahn-intel Mar 24, 2022
4242cb8
[SYCL][ESIMD][EMU]Removing XFAIL for tests enabled with PI_API debug …
dongkyunahn-intel Mar 28, 2022
1f3ab2e
[SYCL] Add tests for some half builtins (#880)
t4c1 Mar 28, 2022
11cb277
[SYCL][ESIMD] Rename tests on USM simd load constructors (#950)
yuriykoch Mar 29, 2022
de1f777
[SYCL][ESIMD] Rename sbarrier => split_barrier (#938)
sndmitriev Mar 29, 2022
8d22c1b
Disable half_builtins test on accelerator devices (#956)
bader Mar 30, 2022
4bea4cc
[SYCL][ESIMD] Add filtration support for type packs (#926)
yuriykoch Mar 30, 2022
266bb74
[SYCL] Add support for device_read_only shared USM allocations (#925)
smaslov-intel Mar 30, 2022
790e85c
[SYCL] Re-enable DiscardEvents/invalid_event.cpp (#960)
Mar 31, 2022
edb565a
Disable Assert/assert_in_simultaneously_multiple_tus.cpp (#959)
kbobrovs Mar 31, 2022
9e43336
[SYCL] Add SYCL lib path to sycl_options after afaefb6 (#957)
vmaksimo Mar 31, 2022
7320db4
Revert "[SYCL] Disable test assert_in_simultaneous_kernels due to fla…
KseniyaTikhomirova Mar 31, 2022
ad6cd42
[SYCL][ESIMD] Add tests for lsc mem access APIs (#817)
sndmitriev Mar 31, 2022
034142e
[SYCL][ESIMD] Add tests on simd load from accessors (#921)
yuriykoch Apr 1, 2022
7c83c66
Test load_store.cpp pass with uplift oclcpu 2022.13.3.0.16 (#951)
yanfeng3721 Apr 1, 2022
e56b622
[SYCL][ESIMD] Fix test for simd broadcast constructor (#966)
vasilytric Apr 1, 2022
b171125
[SYCL][ESIMD][EMU] Running non-ESIMD kernels on esimd_emulator backen…
lsatanov Apr 1, 2022
e184d60
[SYCL] Add test for usm buffer location properties (#955)
sherry-yuan Apr 3, 2022
11417e4
Fix wrong uses of accelerator LIT feature. (#969)
bader Apr 4, 2022
204f53e
[SYCL] [FPGA] Modifying fpga_pipes emulator test (#800)
tyoungsc Apr 5, 2022
5d7d836
[SYCL][CUDA][BFLOAT16] Temp oneapi test file adds unary coverage (#889)
JackAKirk Apr 5, 2022
fd44d02
[SYCL] cmake option for running test with single backend (#972)
dongkyunahn-intel Apr 5, 2022
b064bc8
[SYCL][CUDA] Add tests for exceeding maximum number of work groups (#…
t4c1 Apr 8, 2022
de55390
[SYCL] Test buffer interop for the Level Zero backend (#708)
againull Apr 8, 2022
58b6aa0
[SYCL] Remove accidentally committed files (#981)
againull Apr 8, 2022
67fdfa7
Fix bug (using undefined value) in ESIMD's slm_gather_scatter_rgba.cp…
kbobrovs Apr 11, 2022
8acf00e
[SYCL][XPTI] Added test covering kernel info (#949)
vladimirlaz Apr 12, 2022
6ce8f20
[SYCl][L0] Buffer for multi-device context is using device allocation…
smaslov-intel Apr 12, 2022
c4b7121
Fix batching test for PR 5977 (#978)
asudarsa Apr 12, 2022
b212290
[SYCL] Mark exclusive_scan_over_group.cpp as UNSUPPORTED: ze_debug4 (…
aelovikov-intel Apr 13, 2022
d81e41a
temporarily turning off three tests that seem to fail only on CI syst…
cperkinsintel Apr 13, 2022
afbdd0a
[SYCL][ESIMD] Add test on simd select 2d function (#908)
vasilytric Apr 13, 2022
9337032
[SYCL] Disable ze_debug4 check for L0 buffer interop tests (#992)
againull Apr 14, 2022
edb3ad1
[SYCL][ESIMD] Make oword alignment usage explicit (#965)
yuriykoch Apr 15, 2022
36a78e8
[SYCL] Ownership test for L0 buffer interop requires gpu (#993)
againull Apr 18, 2022
8c5b499
clang-format update for llvm-test-suite (#995)
cperkinsintel Apr 18, 2022
e06cbca
[NFC][CODEOWNERS] Update codeowners (#997)
Apr 18, 2022
165a46d
[SYCL] Adds regression test for PCI address BDF format (#991)
steffenlarsen Apr 19, 2022
f7b4cb1
[SYCL] Split optimization_level_debug_info test (#977)
steffenlarsen Apr 19, 2022
1de20a0
[SYCL] reenabling test in anticipation of GPU uplift (#994)
cperkinsintel Apr 19, 2022
3bd46fd
[SYCL] Add optimized/non-optimized CHECKs for SYCL/XPTI/kernel/* (#1000)
aelovikov-intel Apr 21, 2022
a8db568
[SYCL] Add queue::wait XPTI instrumentation test case (#996)
aelovikov-intel Apr 21, 2022
032f41c
add gpu-intel-dg2 support to available_features. (#990)
myler Apr 22, 2022
6aa6e37
[ESIMD] Split the LIT test dgetrf.cpp to 2 tests to improve test CI t…
v-klochkov Apr 22, 2022
d16c7a7
[ESIMD] Split the test simd_view_select_2d.cpp to 2 tests to reduce C…
v-klochkov Apr 22, 2022
0cedbae
[SYCL] Temporary disable undefined-symbol test (#1007)
cperkinsintel Apr 24, 2022
d1abced
[ESIMD] Removed XFAIL as simd_view-select_2d_int.cpp started passing …
v-klochkov Apr 26, 2022
bb1a99c
[SYCL] Add tests for get_native(buffer) for OpenCL and CUDA backends …
maximdimakov Apr 26, 2022
2b77270
[SYCL] [FPGA] Update latency control E2E tests (#982)
shuoniu-intel Apr 28, 2022
2a19f3b
[SYCL] Add regression test for 0-size local accessors (#1001)
steffenlarsen Apr 29, 2022
5b8908a
[SYCL][CUDA] Reduce required sm version for atomic_ref tests (#985)
t4c1 May 3, 2022
0640465
Update clang-offload-bundler usage (#1011)
mdtoguchi May 3, 2022
89d93f3
[SYCL] Add tests for SYCL2020 queue::parallel_for() shortcuts (#405)
v-klochkov May 3, 2022
ff6000d
[ESIMD] Add test cases for 32-bit accessor based gather/scatter (#1014)
v-klochkov May 3, 2022
7295f7e
[SYCL][ESIMD] Update tests after API changes (#974)
sndmitriev May 3, 2022
c9e9d5f
[SYCL] Now that GPU uplift is done, this test should pass on both CI …
cperkinsintel May 4, 2022
9cf8258
[SYCL] Add tests for span reductions (#1009)
Pennycook May 5, 2022
b40d1e3
Revert "Revert "[SYCL] Enable parallel indexers for AMD, after adding…
vladimirlaz May 5, 2022
422984f
[SYCL][Matrix] add static cast to the half test to correct compilatio…
dkhaldi May 6, 2022
4c36668
[SYCL][L0] Test for pooled small allocations. (#980)
rdeodhar May 6, 2022
c4e3c97
[SYCL] Expand reduction_span XFAIL to all hip backend configs (#1020)
steffenlarsen May 7, 2022
613ede6
[SYCL][Matrix] add a new joint matrix test that uses SYCL bfloat16 (#…
dkhaldi May 9, 2022
5dd32c5
[SYCL] Update tests for half operator (#1012)
AidanBeltonS May 9, 2022
e1a6e78
[ESIMD] Fix rgba smoke test to honor write mask restrictions. (#1023)
kbobrovs May 11, 2022
46a229e
Update tests in preparation for default device instrumentation (#1017)
mdtoguchi May 12, 2022
8fb5c35
[SYCL] Enable fallback assertion test for OpenCL backend (#1026)
againull May 16, 2022
356ccdc
enable unoptimized_stream.cpp for CUDA backend (#1024)
t4c1 May 17, 2022
5b15a63
[ESIMD] Add test for accessor based gather/scatter_rgba (#1022)
v-klochkov May 17, 2022
533dc7a
[SYCL][CUDA] Add tests for asynchronous barrier (#737)
t4c1 May 17, 2022
12fdee6
[SYCL] test needs to ensure partition_equally is supported before exe…
cperkinsintel May 19, 2022
289c2c7
[SYCL][L0] Adds new L0 make_queue input member to interop test (#1025)
steffenlarsen May 19, 2022
139fdc9
[SYCL] Temporarily disable SubGroup/attributes.cpp test for OpenCL CP…
againull May 20, 2022
46354b5
[SYCL] Reenable GroupAlgorithm tests (#1021)
cperkinsintel May 20, 2022
f61938f
[SYCL] Change online compiler test to build IL based on queue (#1028)
steffenlarsen May 23, 2022
a2a254f
[SYCL] Fix resource management in SYCL/Plugin/interop-level-zero.cpp …
aelovikov-intel May 23, 2022
209c1c7
[SYCL][HIP] Mark select group algorithm tests as xfail for hip/amd (#…
cperkinsintel May 23, 2022
8a28d78
Set object extension based on system and not driver used (#1030)
mdtoguchi May 23, 2022
069169a
[SYCL] Add tests for atomic_ref memory orders (#900)
t4c1 May 27, 2022
b10bd8e
[ESIMD] Add more tests for LSC block_load/block_store/gather/scatter …
v-klochkov May 31, 2022
3f55148
[SYCL][ESIMD][EMU] Half-type support (#1044)
dongkyunahn-intel Jun 3, 2022
4c05df0
[SYCL] Adds basic tests for buffer_allocator (#1039)
steffenlarsen Jun 3, 2022
3cf1cc0
[SYCL] Add a test for alignment of allocated USM memory (#1042)
aelovikov-intel Jun 4, 2022
6bf5d74
[SYCL] Add a test with rebound usm_allocator (#1038)
aelovikov-intel Jun 4, 2022
f5faacd
[SYCL] Reduce memory size to reduce test complexity and avoid flaky m…
asudarsa Jun 5, 2022
7f68a81
[SYCL] Set line buffering mode for stderr for some assert tests (#872)
s-kanaev Jun 7, 2022
b2f23de
[SYCL] Re-enable L0 batch test (#1035)
asudarsa Jun 7, 2022
a0456f0
[SYCL] Update to PI_ERROR_INVALID_OPERATION (#1048)
jchlanda Jun 8, 2022
83bbe77
[SYCL][CUDA][Matrix] Adding test case for tf32 (#963)
hdelan Jun 8, 2022
2af10df
[SYCL][matrix] add a new test for irregular slicing on packed matrix …
dkhaldi Jun 9, 2022
7617968
[SYCL] These tests are currently failing on CUDA (#1052)
Jun 9, 2022
1ca16ca
[SYCL][CUDA] Add cuda-experimental context and device test (#1041)
AidanBeltonS Jun 10, 2022
d22b329
[SYCL] Add bf16 aspect (#888)
AidanBeltonS Jun 13, 2022
3236832
[SYCL][CUDA] Add experimental cuda queue interop test (#1054)
AidanBeltonS Jun 15, 2022
edd4388
[SYCL][libdevice] Test libdevice jit-link mode. (#1055)
jinge90 Jun 16, 2022
0108419
[SYCL] Add more GPU options to available features (#1047)
myler Jun 16, 2022
ae5c5e8
[SYCL] test errc for placeholder accessor fail (#890)
cperkinsintel Jun 18, 2022
a84675d
Add cuda event interop test and has_native_event (#1053)
AidanBeltonS Jun 20, 2022
21472dc
[SYCL][CUDA] Re-enable test for samplers (#1062)
pgorlani Jun 21, 2022
6b9e418
enable working tests (#1059)
t4c1 Jun 21, 2022
6646adc
[ESIMD] Add a test to validate new implementation of esimd::fmod (#1045)
fineg74 Jun 22, 2022
ac68994
[SYCL] Change tests for PI errors (#1061)
steffenlarsen Jun 22, 2022
b487206
[ESIMD] Disable fmod_compatibility_test.cpp on esimd_emulator (#1066)
fineg74 Jun 22, 2022
baf3ff5
[SYCL] Use <CL/sycl.hpp> include in recent USM tests (#1065)
aelovikov-intel Jun 22, 2022
258a40d
[SYCL] Add tests for native math extension (#895)
pgorlani Jun 23, 2022
773b61e
[SYCL] Add --ffast-math tests (#919)
pgorlani Jun 24, 2022
3769374
[SYCL][CUDA] Add cuda_dev_kit feature (#1056)
steffenlarsen Jun 27, 2022
50d115d
[SYCL] Ignore backend warning in discard event test (#1050)
steffenlarsen Jun 27, 2022
b24c43c
[SYCL] Don't check for memory leaks in the L0 buffer interop test (#1…
againull Jun 27, 2022
dbe4ce8
[SYCL] Enable asserts for cuda (#1070)
jchlanda Jun 28, 2022
7f0ca80
[ESIMD] Add a test for lsc_fence intrinsic (#1071)
v-klochkov Jun 30, 2022
a94982c
[SYCL][CUDA] Test cases for bfloat16 math/elem wise joint_matrix (#975)
JackAKirk Jun 30, 2022
4936994
[ESIMD] Introduce a test for a fix for copy_to handling of char buffe…
fineg74 Jun 30, 2022
9e8dbec
[SYCL][CUDA] Explicitly adding extension headers in tests. (#1072)
JackAKirk Jul 1, 2022
6569dfc
Fix compilation of tests using printf extension. (#1075)
bader Jul 4, 2022
d970da8
[SYCL][HIP] Mark reduction_span_pack.cpp unsupported on hip/amd (#1079)
dwoodwor-intel Jul 6, 2022
31d333f
[SYCL] Use non-deprecated names in online_compiler_common.hpp (#1080)
aelovikov-intel Jul 8, 2022
b67c7db
[SYCL][CUDA] Enable group tests (#1077)
t4c1 Jul 8, 2022
032f4a1
[SYCL][CUDA] Revert experimental/builtins.hpp includes (#1076)
JackAKirk Jul 11, 2022
ff3c507
[ESIMD] Fix the test verifying printf with ESIMD kernel (#1090)
v-klochkov Jul 13, 2022
cc2cc9b
[SYCL] Change CL/sycl/ to sycl/ (#1078)
aelovikov-intel Jul 13, 2022
f3fad64
[SYCL][L0] re-enable SYCL/Plugin/level_zero_batch_barrier.cpp (#1092)
smaslov-intel Jul 14, 2022
e21a811
[SYCL] Use SYCL_PI_SUPPRESS_ERROR_MESSAGE in simultaneous assert test…
jchlanda Jul 14, 2022
1ea3cc0
[SYCL] Temporarily disable Basic/stream/release_resources_test.cpp (#…
againull Jul 14, 2022
cd495f0
[SYCL][L0] check eager init mode (#1091)
smaslov-intel Jul 14, 2022
eb58c19
[SYCL] [L0] Test for checking use of immediate commandlists. (#1095)
rdeodhar Jul 19, 2022
8e376a1
[ESIMD] Test proper compilation of abs function (#1101)
fineg74 Jul 20, 2022
71c06df
[ESIMD] Add LIT tests for -fsycl-esimd-force-stateless-mem (#1104)
v-klochkov Jul 20, 2022
9d2c047
[SYCL] Removed instances of deprecated feature kernel::get_work_group…
raaiq1 Jul 20, 2022
2466d1c
[SYCL] Add regression test for https://github.com/intel/llvm/pull/646…
aelovikov-intel Jul 22, 2022
597c3a7
[SYCL][ESIMD] Fix test failure when running on emulator (#1109)
fineg74 Jul 23, 2022
cc10e7d
[SYCL][ESIMD][EMU] Enabling dpas_test1/2/3 tests (#1110)
dongkyunahn-intel Jul 26, 2022
0d6600c
[ESIMD] Refresh the test for oneapi::experimental::printf (#1111)
v-klochkov Jul 27, 2022
86df4d0
[SYCL] Add device_global on-device tests (#971)
steffenlarsen Jul 27, 2022
a8a50ef
[ESIMD] Add a test specialization constant that is set but not used (…
v-klochkov Jul 27, 2022
5eeb87e
Revert "[SYCL][ESIMD][EMU] Enabling dpas_test1/2/3 tests (#1110)" (#1…
dongkyunahn-intel Jul 27, 2022
67f591c
[ESIMD][EMU] Disable unused_spec_const test for emulator (#1117)
v-klochkov Jul 28, 2022
d72cc04
[SYCL] Remove SYCL/Regression/kernel_name_inside_sycl_namespace.cpp (…
aelovikov-intel Jul 28, 2022
7a5cb31
[SYCL] Adjust tests to get_native class functions removal (#1113)
sergey-semenov Jul 29, 2022
635fc6c
[NFC][SYCL] Remove explict "cl::" namespace references (#1116)
aelovikov-intel Jul 29, 2022
d8b7396
[SYCL] Add <iostream> headers to tests which assumed "CL/sycl.hpp" wo…
raaiq1 Jul 30, 2022
7a21a8f
[SYCL] Remove missed uses of get_native class functions (#1125)
sergey-semenov Aug 1, 2022
c4d6c14
[SYCL][HIP] Fix assert tests (#1083)
npmiller Aug 2, 2022
abc3d36
[SYCL][HIP] Disable flaky HIP test (#1126)
npmiller Aug 3, 2022
6a07d0e
[SYCL] Disable failing test for CUDA (#1127)
hdelan Aug 3, 2022
42bbc14
[SYCL] Tests for events caching mode in the L0 plugin (#1121)
againull Aug 4, 2022
de2eb4c
[SYCL] Adjust tests to info descriptor changes (#1107)
sergey-semenov Aug 5, 2022
23e8f46
[SYCL] Add E2E invoke_simd 'smoke' test. (#1124)
kbobrovs Aug 5, 2022
9d35612
[SYCL] new tests for SYCL 2020 callable device selector interfaces (#…
cperkinsintel Aug 5, 2022
fd36103
[SYCL][CUDA][HIP] Fix compile command in CommandCleanupThreadSafety.c…
t4c1 Aug 5, 2022
813b2f6
[SYCL][CUDA] Enable printf test for CUDA (#1096)
pgorlani Aug 5, 2022
145b113
[SYCL][CUDA] Fix compile command in gpu.cpp (#1088)
t4c1 Aug 5, 2022
b57e11f
[SYCL][CUDA][HIP] Fix device_num.cpp test (#1081)
t4c1 Aug 5, 2022
d5d594f
[SYCL][CUDA] Fix kernel bundle related tests (#1093)
t4c1 Aug 5, 2022
8756be6
[SYCL] Enable reduction_nd_n_vars test (#1133)
KseniyaTikhomirova Aug 8, 2022
b061789
[SYCL] Enable reduction tests back (LevelZero GPU RT was updated) (#1…
KseniyaTikhomirova Aug 8, 2022
2c6eb63
[SYCL][CUDA][HIP] Expand Config/select_device.cpp for CUDA and HIP (#…
sami-hatna66 Aug 9, 2022
bdd8cc4
[SYCL][HIP] Disable device_num.cpp (#1136)
t4c1 Aug 9, 2022
fec22e4
Test for changes to ensure proper compilation of bitshift functions (…
fineg74 Aug 9, 2022
7e0c477
[SYCL] Enable assert_in_simultaneously_multiple_tus back for LevelZer…
KseniyaTikhomirova Aug 10, 2022
dafd0f6
[SYCL] Use 0 for generic mem_advise (#1140)
steffenlarsen Aug 10, 2022
1f66a4f
[SYCL] Update get_profiling_info() test (#1120)
raaiq1 Aug 10, 2022
66c65ac
[SYCL][L0] check fixed queue indices when submitting to sub-sub-devic…
smaslov-intel Aug 10, 2022
a4f2cae
[SYCL] Adjust SYCL 2020 guarded feature tests (#1137)
steffenlarsen Aug 11, 2022
daad7c2
[SYCL] Complementary change for removing cl:: namespace (#1128)
aelovikov-intel Aug 11, 2022
9282530
[SYCL] E2E test for code_location. (#1123)
cperkinsintel Aug 11, 2022
f05f8e0
[SYCL] disable code_loc e2e test on hip and cuda (#1145)
cperkinsintel Aug 12, 2022
be1de4c
Add regression test for DAE and separate compile (#970)
AlexeySachkov Aug 12, 2022
b1e3dad
[SYCL][HIP] Enable reduction span test (#1097)
pgorlani Aug 12, 2022
2fb0a0e
[SYCL][HIP] Re-enable aspect::atomic64 tests (#1094)
pgorlani Aug 12, 2022
713a078
[SYCL] new tests for SYCL 2020 standalone device selectors ( gpu_sele…
cperkinsintel Aug 12, 2022
b1d9a04
[libdevice] Add tests for imf simd APIs. (#1074)
jinge90 Aug 15, 2022
bf08859
[SYCL] Disable recently added test on CUDA/HIP (#1148)
Aug 16, 2022
e7db723
[SYCL] Enable Assert/assert_in_simultaneously_multiple_tus.cpp for L0…
againull Aug 16, 2022
58ceaa1
[SYCL][XPTI] Increase number of expected args in reduction (#1040)
steffenlarsen Aug 16, 2022
9a21c9f
Make epsilon comparison for double type
fineg74 Aug 26, 2022
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34 changes: 34 additions & 0 deletions .github/CODEOWNERS
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* @pvchupin

# Use runtime team as the umbrella for most of the tests
/SYCL/ @intel/llvm-reviewers-runtime

# SYCL sub-directory matchers are grouped by code owner first, followed by
# alphabetical order within the group. Please, keep this ordering.

# Group algorithms
/SYCL/GroupAlgorithm/ @Pennycook @intel/llvm-reviewers-runtime
/SYCL/GroupLocalMemory/ @Pennycook @intel/llvm-reviewers-runtime
/SYCL/SubGroup/ @Pennycook @intel/llvm-reviewers-runtime
/SYCL/SubGroupMask/ @Pennycook @intel/llvm-reviewers-runtime

# Plugin interface for Level Zero
/SYCL/Plugin/*level-zero* @intel/dpcpp-l0-pi-reviewers
/SYCL/Plugin/*level_zero* @intel/dpcpp-l0-pi-reviewers

# Explicit SIMD
/SYCL/ESIMD/ @intel/dpcpp-esimd-reviewers

# BFloat16 conversion
/SYCL/BFloat16/ @intel/dpcpp-tools-reviewers

# Compiler tests
/SYCL/AOT/ @intel/dpcpp-tools-reviewers
/SYCL/DeviceCodeSplit/ @intel/dpcpp-tools-reviewers
/SYCL/SeparateCompile/ @intel/dpcpp-tools-reviewers

# Printf
/SYCL/Printf/ @intel/dpcpp-tools-reviewers

# Specialization constant
/SYCL/SpecConstants/ @intel/dpcpp-tools-reviewers
34 changes: 34 additions & 0 deletions .github/workflows/clang-format.yml
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name: clang-format-check

on:
pull_request:
branches:
- intel

jobs:
build:
runs-on: ubuntu-latest

container:
image: ghcr.io/intel/llvm/sycl_ubuntu2004_nightly:no-drivers

steps:
- uses: actions/checkout@v2
with:
fetch-depth: 2

- name: Run clang-format for the patch
shell: bash {0}
run: |
git config --global --add safe.directory /__w/llvm-test-suite/llvm-test-suite
git clang-format ${GITHUB_SHA}^1
git diff > ./clang-format.patch

# Add patch with formatting fixes to CI job artifacts
- uses: actions/upload-artifact@v1
with:
name: clang-format-patch
path: ./clang-format.patch

- name: Check if clang-format patch is empty
run: bash -c "if [ -s ./clang-format.patch ]; then cat ./clang-format.patch; exit 1; fi"
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,4 @@
# External/*
/test-suite-externals
*.pyc
/build*
88 changes: 88 additions & 0 deletions CONTRIBUTING.md
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@@ -0,0 +1,88 @@
# Contributing

## License

This project is licensed under the terms of the Apache License v2.0 with LLVM
Exceptions license ([LICENSE.txt](LICENSE.TXT)) to ensure our ability to
contribute this project to the LLVM test suite project under the same license.

By contributing to this project, you agree to the Apache License v2.0 with LLVM
Exceptions and copyright terms there in and release your contribution under
these terms.

## Contribution process

### Development

For any changes not related to DPC++, but rather to LLVM in general, it is
strongly encouraged that you submit the patch to https://github.com/llvm/llvm-test-suite directly.
See [LLVM contribution guidelines](https://llvm.org/docs/Contributing.html)
for more information.

- Create a personal fork of the project on GitHub
- For the DPC++ end-to-end test development, use **intel** branch as baseline
for your changes.
- Prepare your patch
- follow [LLVM coding standards](https://llvm.org/docs/CodingStandards.html)
- [clang-format](https://clang.llvm.org/docs/ClangFormat.html) and
[clang-tidy](https://clang.llvm.org/extra/clang-tidy/) tools can be
integrated into your workflow to ensure formatting and stylistic
compliance of your changes.
- use

```bash
wget https://raw.githubusercontent.com/intel/llvm/sycl/clang/tools/clang-format/git-clang-format
python git-clang-format `git merge-base origin/intel HEAD`
```

to check the format of your current changes against the `origin/intel`
branch.
- `-f` to also correct unstaged changes
- `--diff` to only print the diff without applying

### Testing

- See [SYCL/README.md](SYCL/README.md) for instructions.

### Commit message

- When writing your commit message, please make sure to follow
[LLVM developer policies](
https://llvm.org/docs/DeveloperPolicy.html#commit-messages) on the subject.
- For any DPC++-related commit, the `[SYCL]` tag should be present in the
commit message title. To a reasonable extent, additional tags can be used
to signify the component changed, e.g.: `[LIT]`, `[NFC]`, `[Doc]`.

### Review and acceptance testing

- Create a pull request for your changes following [Creating a pull request
instructions](https://help.github.com/articles/creating-a-pull-request/).
- PR description should follow same rules as commit message. It is used as
commit message on the final merge.
- Changes addressing comments made during code review should be added as a
separate commits to the same PR.
- CI will run checks which are prerequisites for submitting PR:
- clang-format-check/build checks that the patch matches coding style
(see [clang-format](https://clang.llvm.org/docs/ClangFormat.html));
- Jenkins/pre-ci-cuda - runs all related tests on CUDA backend for GPU device
on Ubuntu 18.04;
- Jenkins/pre-ci-linux - runs all related tests on Ubuntu 18.04 machine with
Level_Zero backend (GPU device) and OpenCL backend (CPU, GPU and FPGA
emulator devices);
- Jenkins/pre-ci-windows - runs all related tests on Windows Server 2019 with
Level_Zero backend (GPU device) and OpenCL backend (CPU, GPU and FPGA
emulator devices).

The last three checks are done for the latest available nightly build for DPC++
compiler and runtime from [intel/llvm](https://github.com/intel/llvm). The
build happens around 18:00 UTC if there are new commits since previous build.

Once the PR is approved and all checks have passed, the pull request is
ready for merge.

### Merge

Project maintainers merge pull requests by "Squash and merge". PR description
is used as final commit message.

\*Other names and brands may be claimed as the property of others.
27 changes: 27 additions & 0 deletions README.md
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# LLVM* test suite repository

Please see the LLVM testing infrastructure guide:

https://llvm.org/docs/TestSuiteGuide.html

for more information on the contents of this repository.

## Introduction

Intel staging area for LLVM test suite contribution. Home for oneAPI Data
Parallel C++ compiler tests extending LLVM test suite.

## License

See [LICENSE.txt](LICENSE.TXT) for details.

## Contributing

See [CONTRIBUTING.md](CONTRIBUTING.md) for details.

## Related projects documentation

* oneAPI Data Parallel C++ compiler - See
[DPC++ Documentation](https://intel.github.io/llvm-docs/)

\*Other names and brands may be claimed as the property of others.
2 changes: 2 additions & 0 deletions SYCL/.clang-format
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BasedOnStyle: LLVM
CommentPragmas: "(RUN|FAIL|REQUIRES|UNSUPPORTED|CHECK[A-Za-z0-9_-]*) *:|expected-"
74 changes: 74 additions & 0 deletions SYCL/AOT/Inputs/aot.cpp
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//==--- aot.cpp - Simple vector addition (AOT compilation example) --------==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===---------------------------------------------------------------------===//

#include <sycl/sycl.hpp>

#include <array>
#include <iostream>

constexpr sycl::access::mode sycl_read = sycl::access::mode::read;
constexpr sycl::access::mode sycl_write = sycl::access::mode::write;

template <typename T> class SimpleVadd;

template <typename T, size_t N>
void simple_vadd(const std::array<T, N> &VA, const std::array<T, N> &VB,
std::array<T, N> &VC) {
sycl::queue deviceQueue([](sycl::exception_list ExceptionList) {
for (std::exception_ptr ExceptionPtr : ExceptionList) {
try {
std::rethrow_exception(ExceptionPtr);
} catch (sycl::exception &E) {
std::cerr << E.what();
} catch (...) {
std::cerr << "Unknown async exception was caught." << std::endl;
}
}
});

sycl::range<1> numOfItems{N};
sycl::buffer<T, 1> bufferA(VA.data(), numOfItems);
sycl::buffer<T, 1> bufferB(VB.data(), numOfItems);
sycl::buffer<T, 1> bufferC(VC.data(), numOfItems);

deviceQueue.submit([&](sycl::handler &cgh) {
auto accessorA = bufferA.template get_access<sycl_read>(cgh);
auto accessorB = bufferB.template get_access<sycl_read>(cgh);
auto accessorC = bufferC.template get_access<sycl_write>(cgh);

cgh.parallel_for<class SimpleVadd<T>>(numOfItems, [=](sycl::id<1> wiID) {
accessorC[wiID] = accessorA[wiID] + accessorB[wiID];
});
});

deviceQueue.wait_and_throw();
}

int main() {
const size_t array_size = 4;
std::array<sycl::cl_int, array_size> A = {{1, 2, 3, 4}}, B = {{1, 2, 3, 4}},
C;
std::array<sycl::cl_float, array_size> D = {{1.f, 2.f, 3.f, 4.f}},
E = {{1.f, 2.f, 3.f, 4.f}}, F;
simple_vadd(A, B, C);
simple_vadd(D, E, F);
for (unsigned int i = 0; i < array_size; i++) {
if (C[i] != A[i] + B[i]) {
std::cout << "The results are incorrect (element " << i << " is " << C[i]
<< "!\n";
return 1;
}
if (F[i] != D[i] + E[i]) {
std::cout << "The results are incorrect (element " << i << " is " << F[i]
<< "!\n";
return 1;
}
}
std::cout << "The results are correct!\n";
return 0;
}
12 changes: 12 additions & 0 deletions SYCL/AOT/accelerator.cpp
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//=-- accelerator.cpp - compilation for fpga emulator dev using opencl-aot --=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===---------------------------------------------------------------------===//

// REQUIRES: opencl-aot, accelerator

// RUN: %clangxx -fsycl -fsycl-targets=spir64_fpga %S/Inputs/aot.cpp -o %t.out
// RUN: %ACC_RUN_PLACEHOLDER %t.out
15 changes: 15 additions & 0 deletions SYCL/AOT/cpu.cpp
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@@ -0,0 +1,15 @@
//==--- cpu.cpp - AOT compilation for cpu devices using opencl-aot --------==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===---------------------------------------------------------------------===//

// REQUIRES: opencl-aot, cpu

// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64 %S/Inputs/aot.cpp -o %t.out
// RUN: %CPU_RUN_PLACEHOLDER %t.out

// Test that opencl-aot can handle multiple build options.
// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64 %S/Inputs/aot.cpp -Xsycl-target-backend "--bo=-g" -Xsycl-target-backend "--bo=-cl-opt-disable" -o %t2.out
14 changes: 14 additions & 0 deletions SYCL/AOT/gpu.cpp
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@@ -0,0 +1,14 @@
//==--- gpu.cpp - AOT compilation for gen devices using GEN compiler ------==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===---------------------------------------------------------------------===//

// REQUIRES: ocloc, gpu
// UNSUPPORTED: cuda
// CUDA is not compatible with SPIR.
//
// RUN: %clangxx -fsycl -fsycl-targets=spir64_gen -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %S/Inputs/aot.cpp -o %t.out
// RUN: %GPU_RUN_PLACEHOLDER %t.out
60 changes: 60 additions & 0 deletions SYCL/AOT/multiple-devices.cpp
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@@ -0,0 +1,60 @@
//==-- multiple-devices.cpp - Appropriate AOT-compiled image selection -----==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

// REQUIRES: opencl-aot, ocloc, cpu, gpu, accelerator
// UNSUPPORTED: cuda
// CUDA is not compatible with SPIR.

// Produce a fat object for all targets (generic SPIR-V, CPU, GPU, FPGA)
// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_x86_64,spir64_gen,spir64_fpga %S/Inputs/aot.cpp -c -o %t.o

// CPU, GPU, FPGA
// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_all_aot.out
// RUN: %HOST_RUN_PLACEHOLDER %t_all_aot.out
// RUN: %CPU_RUN_PLACEHOLDER %t_all_aot.out
// RUN: %GPU_RUN_PLACEHOLDER %t_all_aot.out
// RUN: %ACC_RUN_PLACEHOLDER %t_all_aot.out

// CPU, GPU
// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_gen -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_cpu_gpu.out
// RUN: %HOST_RUN_PLACEHOLDER %t_cpu_gpu.out
// RUN: %CPU_RUN_PLACEHOLDER %t_cpu_gpu.out
// RUN: %GPU_RUN_PLACEHOLDER %t_cpu_gpu.out

// CPU, FPGA
// RUN: %clangxx -fsycl -fsycl-targets=spir64_x86_64,spir64_fpga %t.o -o %t_cpu_fpga.out
// RUN: %HOST_RUN_PLACEHOLDER %t_cpu_fpga.out
// RUN: %CPU_RUN_PLACEHOLDER %t_cpu_fpga.out
// RUN: %ACC_RUN_PLACEHOLDER %t_cpu_fpga.out

// GPU, FPGA
// RUN: %clangxx -fsycl -fsycl-targets=spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_gpu_fpga.out
// RUN: %HOST_RUN_PLACEHOLDER %t_gpu_fpga.out
// RUN: %GPU_RUN_PLACEHOLDER %t_gpu_fpga.out
// RUN: %ACC_RUN_PLACEHOLDER %t_gpu_fpga.out

// No AOT-compiled image for CPU
// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_gen,spir64_fpga -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_spv_gpu_fpga.out
// RUN: %CPU_RUN_PLACEHOLDER %t_spv_gpu_fpga.out
// Check that execution on AOT-compatible devices is unaffected
// RUN: %GPU_RUN_PLACEHOLDER %t_spv_gpu_fpga.out
// RUN: %ACC_RUN_PLACEHOLDER %t_spv_gpu_fpga.out

// No AOT-compiled image for GPU
// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_x86_64,spir64_fpga %t.o -o %t_spv_cpu_fpga.out
// RUN: %GPU_RUN_PLACEHOLDER %t_spv_cpu_fpga.out
// Check that execution on AOT-compatible devices is unaffected
// RUN: %CPU_RUN_PLACEHOLDER %t_spv_cpu_fpga.out
// RUN: %ACC_RUN_PLACEHOLDER %t_spv_cpu_fpga.out

// No AOT-compiled image for FPGA
// RUN: %clangxx -fsycl -fsycl-targets=spir64,spir64_x86_64,spir64_gen -Xsycl-target-backend=spir64_gen %gpu_aot_target_opts %t.o -o %t_spv_cpu_gpu.out
// RUN: %ACC_RUN_PLACEHOLDER %t_spv_cpu_gpu.out
// Check that execution on AOT-compatible devices is unaffected
// RUN: %CPU_RUN_PLACEHOLDER %t_spv_cpu_gpu.out
// RUN: %GPU_RUN_PLACEHOLDER %t_spv_cpu_gpu.out
17 changes: 17 additions & 0 deletions SYCL/AOT/with-llvm-bc.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
//==----- with-llvm-bc.cpp - SYCL kernel with LLVM IR bitcode as binary ----==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

// REQUIRES: cpu, dump_ir

// RUN: %clangxx -fsycl -fsycl-targets=spir64 -c %S/Inputs/aot.cpp -o %t.o
// RUN: %clangxx -fsycl -fsycl-link-targets=spir64 %t.o -o %t.spv
// RUN: llvm-spirv -r %t.spv -o %t.bc
// RUN: %clangxx -fsycl -fsycl-add-targets=spir64:%t.bc %t.o -o %t.out
//
// Only CPU supports LLVM IR bitcode as a binary
// RUN: %CPU_RUN_PLACEHOLDER %t.out
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