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[AArch64] Fix v4i8 loads in strict-align mode. #95828

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Merged
merged 1 commit into from
Jun 18, 2024
Merged

[AArch64] Fix v4i8 loads in strict-align mode. #95828

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4 changes: 4 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6406,6 +6406,10 @@ SDValue AArch64TargetLowering::LowerLOAD(SDValue Op,
if (LoadNode->getMemoryVT() != MVT::v4i8)
return SDValue();

// Avoid generating unaligned loads.
if (Subtarget->requiresStrictAlign() && LoadNode->getAlign() < Align(4))
return SDValue();

unsigned ExtType;
if (LoadNode->getExtensionType() == ISD::SEXTLOAD)
ExtType = ISD::SIGN_EXTEND;
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47 changes: 47 additions & 0 deletions llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
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Expand Up @@ -450,3 +450,50 @@ define <4 x i8> @bitcast(i32 %0) {
%2 = bitcast i32 %0 to <4 x i8>
ret <4 x i8> %2
}

define <4 x i8> @strict_align_aligned(ptr %v4i8_ptr) "target-features"="+strict-align" {
; CHECK-LE-LABEL: strict_align_aligned:
; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ldr s0, [x0]
; CHECK-LE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: strict_align_aligned:
; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ldr s0, [x0]
; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
; CHECK-BE-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: rev64 v0.4h, v0.4h
; CHECK-BE-NEXT: ret
%v4i8 = load <4 x i8>, ptr %v4i8_ptr, align 4
ret <4 x i8> %v4i8
}

define <4 x i8> @strict_align_unaligned(ptr %v4i8_ptr) "target-features"="+strict-align" {
; CHECK-LE-LABEL: strict_align_unaligned:
; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ld1 { v0.b }[0], [x0]
; CHECK-LE-NEXT: add x8, x0, #1
; CHECK-LE-NEXT: ld1 { v0.b }[2], [x8]
; CHECK-LE-NEXT: add x8, x0, #2
; CHECK-LE-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-LE-NEXT: add x8, x0, #3
; CHECK-LE-NEXT: ld1 { v0.b }[6], [x8]
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: strict_align_unaligned:
; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ld1 { v0.b }[0], [x0]
; CHECK-BE-NEXT: add x8, x0, #1
; CHECK-BE-NEXT: ld1 { v0.b }[2], [x8]
; CHECK-BE-NEXT: add x8, x0, #2
; CHECK-BE-NEXT: ld1 { v0.b }[4], [x8]
; CHECK-BE-NEXT: add x8, x0, #3
; CHECK-BE-NEXT: ld1 { v0.b }[6], [x8]
; CHECK-BE-NEXT: rev64 v0.4h, v0.4h
; CHECK-BE-NEXT: ret
%v4i8 = load <4 x i8>, ptr %v4i8_ptr, align 1
ret <4 x i8> %v4i8
}