Skip to content

[LoongArch] Fix incorrect logic in isLegalAddressingMode() #88694

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Apr 15, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 7 additions & 8 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4876,28 +4876,27 @@ bool LoongArchTargetLowering::isLegalAddressingMode(const DataLayout &DL,
if (AM.BaseGV)
return false;

// Require a 12 or 14 bit signed offset.
if (!isInt<12>(AM.BaseOffs) || !isShiftedInt<14, 2>(AM.BaseOffs))
// Require a 12-bit signed offset or 14-bit signed offset left-shifted by 2
// with `UAL` feature.
if (!isInt<12>(AM.BaseOffs) &&
!(isShiftedInt<14, 2>(AM.BaseOffs) && Subtarget.hasUAL()))
return false;

switch (AM.Scale) {
case 0:
// "i" is not allowed.
if (!AM.HasBaseReg)
return false;
// Otherwise we have "r+i".
// "r+i" or just "i", depending on HasBaseReg.
break;
case 1:
// "r+r+i" is not allowed.
if (AM.HasBaseReg && AM.BaseOffs != 0)
if (AM.HasBaseReg && AM.BaseOffs)
return false;
// Otherwise we have "r+r" or "r+i".
break;
case 2:
// "2*r+r" or "2*r+i" is not allowed.
if (AM.HasBaseReg || AM.BaseOffs)
return false;
// Otherwise we have "r+r".
// Allow "2*r" as "r+r".
break;
default:
return false;
Expand Down
14 changes: 5 additions & 9 deletions llvm/test/CodeGen/LoongArch/gep-imm.ll
Original file line number Diff line number Diff line change
Expand Up @@ -4,23 +4,19 @@
define void @test(ptr %sp, ptr %t, i32 %n) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld.d $a0, $a0, 0
; CHECK-NEXT: move $a3, $zero
; CHECK-NEXT: ld.d $a4, $a0, 0
; CHECK-NEXT: lu12i.w $a0, 1
; CHECK-NEXT: ori $a5, $a0, 3904
; CHECK-NEXT: add.d $a0, $a1, $a5
; CHECK-NEXT: add.d $a1, $a4, $a5
; CHECK-NEXT: addi.w $a2, $a2, 0
; CHECK-NEXT: addi.w $a4, $a3, 0
; CHECK-NEXT: bge $a4, $a2, .LBB0_2
; CHECK-NEXT: .p2align 4, , 16
; CHECK-NEXT: .LBB0_1: # %while_body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: addi.d $a4, $a3, 1
; CHECK-NEXT: st.w $a4, $a1, 0
; CHECK-NEXT: st.w $a3, $a1, 4
; CHECK-NEXT: st.w $a4, $a0, 0
; CHECK-NEXT: st.w $a3, $a0, 4
; CHECK-NEXT: stptr.w $a4, $a0, 8000
; CHECK-NEXT: stptr.w $a3, $a0, 8004
; CHECK-NEXT: stptr.w $a4, $a1, 8000
; CHECK-NEXT: stptr.w $a3, $a1, 8004
; CHECK-NEXT: move $a3, $a4
; CHECK-NEXT: addi.w $a4, $a3, 0
; CHECK-NEXT: blt $a4, $a2, .LBB0_1
Expand Down
Loading