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[RISCV][clang] Don't enable -mrelax-all for -O0 on RISC-V #88538

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Merged
merged 2 commits into from
Apr 22, 2024
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[RISCV][clang] Don't enable -mrelax-all for -O0 on RISC-V #88538

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a27600b
[RISCV][clang] Don't enable -mrelax-all for -O0 on RISC-V
topperc Apr 12, 2024
fa76e26
fixup! update test
topperc Apr 19, 2024
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10 changes: 10 additions & 0 deletions clang/lib/Driver/ToolChains/Clang.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -844,6 +844,16 @@ static bool UseRelaxAll(Compilation &C, const ArgList &Args) {
if (Arg *A = Args.getLastArg(options::OPT_O_Group))
RelaxDefault = A->getOption().matches(options::OPT_O0);

// RISC-V requires an indirect jump for offsets larger than 1MiB. This cannot
// be done by assembler branch relaxation as it needs a free temporary
// register. Because of this, branch relaxation is handled by a MachineIR
// pass before the assembler. Forcing assembler branch relaxation for -O0
// makes the MachineIR branch relaxation inaccurate and it will miss cases
// where an indirect branch is necessary. To avoid this issue we are
// sacrificing the compile time improvement of using -mrelax-all for -O0.
if (C.getDefaultToolChain().getTriple().isRISCV())
RelaxDefault = false;

if (RelaxDefault) {
RelaxDefault = false;
for (const auto &Act : C.getActions()) {
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8 changes: 7 additions & 1 deletion clang/test/Driver/integrated-as.c
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@@ -1,10 +1,16 @@
// XFAIL: target={{.*}}-aix{{.*}}

// RUN: %clang -### -c -save-temps -integrated-as %s 2>&1 | FileCheck %s
// RUN: %clang -### -c -save-temps -integrated-as --target=x86_64 %s 2>&1 | FileCheck %s

// CHECK: cc1as
// CHECK: -mrelax-all

// RISC-V does not enable -mrelax-all
// RUN: %clang -### -c -save-temps -integrated-as --target=riscv64 %s 2>&1 | FileCheck %s -check-prefix=RISCV-RELAX

// RISCV-RELAX: cc1as
// RISCV-RELAX-NOT: -mrelax-all

// RUN: %clang -### -fintegrated-as -c -save-temps %s 2>&1 | FileCheck %s -check-prefix FIAS

// FIAS: cc1as
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