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[RISCV][WIP] Add validation of SPIMM for cm.push/pop. #84989

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Mar 28, 2024
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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -297,7 +297,8 @@ enum OperandType : unsigned {
OPERAND_RVKRNUM_0_7,
OPERAND_RVKRNUM_1_10,
OPERAND_RVKRNUM_2_14,
OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
OPERAND_SPIMM,
OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2050,6 +2050,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_RVKRNUM_2_14:
Ok = Imm >= 2 && Imm <= 14;
break;
case RISCVOp::OPERAND_SPIMM:
Ok = (Imm & 0xf) == 0;
break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
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6 changes: 4 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
Original file line number Diff line number Diff line change
Expand Up @@ -71,10 +71,11 @@ def rlist : Operand<OtherVT> {
}];
}

def stackadj : Operand<OtherVT> {
def stackadj : RISCVOp<OtherVT> {
let ParserMatchClass = StackAdjAsmOperand;
let PrintMethod = "printStackAdj";
let DecoderMethod = "decodeZcmpSpimm";
let OperandType = "OPERAND_SPIMM";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
Expand All @@ -83,10 +84,11 @@ def stackadj : Operand<OtherVT> {
}];
}

def negstackadj : Operand<OtherVT> {
def negstackadj : RISCVOp<OtherVT> {
let ParserMatchClass = NegStackAdjAsmOperand;
let PrintMethod = "printNegStackAdj";
let DecoderMethod = "decodeZcmpSpimm";
let OperandType = "OPERAND_SPIMM";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
Expand Down