[RISCV][WIP] Add validation of SPIMM for cm.push/pop.

[topperc]

This checks the immediate is aligned which would catch what #84935 is fixing

Obviously this will fail tests until the issues are fixed.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

This checks the immediate is aligned which would catch what #83457 is fixing

Obviously this will fail tests until the issues are fixed.

---

Full diff: https://github.com/llvm/llvm-project/pull/84989.diff

3 Files Affected:

• (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+2-1)
• (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+3)
• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZc.td (+2-1)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 6d0381c30d3e86..80f6ad9bb8aefe 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -297,7 +297,8 @@ enum OperandType : unsigned {
   OPERAND_RVKRNUM_0_7,
   OPERAND_RVKRNUM_1_10,
   OPERAND_RVKRNUM_2_14,
-  OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
+  OPERAND_SPIMM,
+  OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM,
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli
   // or vsetivli.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 37a8079dcbf10d..15453a5c5e5924 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2050,6 +2050,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         case RISCVOp::OPERAND_RVKRNUM_2_14:
           Ok = Imm >= 2 && Imm <= 14;
           break;
+        case RISCVOp::OPERAND_SPIMM:
+          Ok = (Imm & 0xf) == 0;
+          break;
         }
         if (!Ok) {
           ErrInfo = "Invalid immediate";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 2c8451c5c4ceb2..b66c28f9fd54ef 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -61,10 +61,11 @@ def rlist : Operand<OtherVT> {
   }];
  }
 
-def spimm : Operand<OtherVT> {
+def spimm : RISCVOp<OtherVT> {
   let ParserMatchClass = SpimmAsmOperand;
   let PrintMethod = "printSpimm";
   let DecoderMethod = "decodeZcmpSpimm";
+  let OperandType = "OPERAND_SPIMM";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))

[wangpc-pp]

LGTM.
(I think you copied the wrong PR ID :-))

[nemanjai]

LGTM. Just an idea - perhaps we should have a test or two with non-multiples of 16 in test/MC/RISCV/rv{64|32}zcmp-invalid.s

[topperc]

LGTM. (I think you copied the wrong PR ID :-))

I definitely did. Fixed