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[AMDGPU] Fix nondeterminism in SIFixSGPRCopies #70644

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Merged
merged 5 commits into from
Oct 31, 2023
Merged

[AMDGPU] Fix nondeterminism in SIFixSGPRCopies #70644

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bfc7b20
Precommit test
jayfoad Oct 30, 2023
aa050e8
[AMDGPU] Fix nondeterminism in SIFixSGPRCopies
jayfoad Oct 30, 2023
0903f3f
Add a TODO comment
jayfoad Oct 31, 2023
c54bda9
Update tests
jayfoad Oct 31, 2023
dd84634
Merge remote-tracking branch 'origin/main' into iterate-sifixsgprcopies
jayfoad Oct 31, 2023
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ class SIFixSGPRCopies : public MachineFunctionPass {
SmallVector<MachineInstr*, 4> PHINodes;
SmallVector<MachineInstr*, 4> S2VCopies;
unsigned NextVGPRToSGPRCopyID;
DenseMap<unsigned, V2SCopyInfo> V2SCopies;
MapVector<unsigned, V2SCopyInfo> V2SCopies;
DenseMap<MachineInstr *, SetVector<unsigned>> SiblingPenalty;

public:
Expand Down Expand Up @@ -988,7 +988,7 @@ bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
for (auto J : Info->Siblings) {
auto InfoIt = V2SCopies.find(J);
if (InfoIt != V2SCopies.end()) {
MachineInstr *SiblingCopy = InfoIt->getSecond().Copy;
MachineInstr *SiblingCopy = InfoIt->second.Copy;
if (SiblingCopy->isImplicitDef())
// the COPY has already been MoveToVALUed
continue;
Expand Down Expand Up @@ -1023,12 +1023,12 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
unsigned CurID = LoweringWorklist.pop_back_val();
auto CurInfoIt = V2SCopies.find(CurID);
if (CurInfoIt != V2SCopies.end()) {
V2SCopyInfo C = CurInfoIt->getSecond();
V2SCopyInfo C = CurInfoIt->second;
LLVM_DEBUG(dbgs() << "Processing ...\n"; C.dump());
for (auto S : C.Siblings) {
auto SibInfoIt = V2SCopies.find(S);
if (SibInfoIt != V2SCopies.end()) {
V2SCopyInfo &SI = SibInfoIt->getSecond();
V2SCopyInfo &SI = SibInfoIt->second;
LLVM_DEBUG(dbgs() << "Sibling:\n"; SI.dump());
if (!SI.NeedToBeConvertedToVALU) {
SI.SChain.set_subtract(C.SChain);
Expand Down
52 changes: 52 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
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@@ -0,0 +1,52 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s

define amdgpu_gs void @f(i32 inreg %arg, i32 %arg1, i32 %arg2) {
; CHECK-LABEL: f:
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_cmp_eq_u32 s0, 0
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %bb3
; CHECK-NEXT: v_mov_b32_e32 v5, v0
; CHECK-NEXT: s_branch .LBB0_3
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: v_mov_b32_e32 v5, 1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: .LBB0_3: ; %bb4
; CHECK-NEXT: v_mov_b32_e32 v6, 0
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: s_mov_b32 s2, s0
; CHECK-NEXT: s_mov_b32 s3, s0
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_mov_b32_e32 v7, v6
; CHECK-NEXT: v_mov_b32_e32 v8, v6
; CHECK-NEXT: v_mov_b32_e32 v2, v6
; CHECK-NEXT: v_mov_b32_e32 v3, v6
; CHECK-NEXT: v_mov_b32_e32 v4, v6
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: buffer_store_b128 v[5:8], v6, s[0:3], 0 idxen
; CHECK-NEXT: buffer_store_b128 v[1:4], v6, s[0:3], 0 idxen
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; CHECK-NEXT: s_endpgm
bb:
%i = icmp eq i32 %arg, 0
br i1 %i, label %bb4, label %bb3

bb3:
br label %bb4

bb4:
%i5 = phi i32 [ %arg1, %bb3 ], [ 1, %bb ]
%i6 = phi i32 [ %arg2, %bb3 ], [ 0, %bb ]
%i7 = insertelement <4 x i32> zeroinitializer, i32 %i5, i64 0
%i8 = bitcast <4 x i32> %i7 to <4 x float>
call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %i8, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)
%i9 = insertelement <4 x i32> zeroinitializer, i32 %i6, i64 0
%i10 = bitcast <4 x i32> %i9 to <4 x float>
call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %i10, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)
ret void
}

declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg)