[M68k] Fix reverse BTST condition causing opposite failure/success logic

[dansalvato]

Given the test case:

define fastcc i16 @testbtst(i16 %a) nounwind {
  entry:
    switch i16 %a, label %no [
      i16 11, label %yes
      i16 10, label %yes
      i16 9, label %yes
      i16 4, label %yes
      i16 3, label %yes
      i16 2, label %yes
    ]

  yes:
    ret i16 1

  no:
    ret i16 0
}

We currently get this result:

testbtst:                               ; @testbtst
; %bb.0:                                ; %entry
	move.l	%d0, %d1
	and.l	#65535, %d1
	sub.l	#11, %d1
	bhi	.LBB0_3
; %bb.1:                                ; %entry
	and.l	#65535, %d0
	move.l	#3612, %d1
	btst	%d0, %d1
	bne	.LBB0_3        ; <------- Erroneous condition
; %bb.2:                                ; %yes
	moveq	#1, %d0
	rts
.LBB0_3:                                ; %no
	moveq	#0, %d0
	rts

The cause of this is a line that explicitly reverses the btst condition code. But on M68k, btst sets condition codes the same as and with a bitmask, meaning EQ indicates failure (bit is zero) and not success, so the condition does not need to be reversed.

In my testing, I've only been able to get switch statements to lower to btst, so I wasn't able to explicitly test other options for lowering. But (if possible to trigger) I believe they have the same logical error. For example, in LowerAndToBTST(), a comment specifies that it's lowering a case where the and result is compared against zero, which means the corresponding btst condition should also not be reversed.

This patch simply flips the ternary expression in getBitTestCondition() to match the ISD condition code with the same M68k code, instead of the opposite.

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[llvmbot]

@llvm/pr-subscribers-backend-m68k

Author: Dan Salvato (dansalvato)

Changes

Given the test case:

define fastcc i16 @<!-- -->testbtst(i16 %a) nounwind {
  entry:
    switch i16 %a, label %no [
      i16 11, label %yes
      i16 10, label %yes
      i16 9, label %yes
      i16 4, label %yes
      i16 3, label %yes
      i16 2, label %yes
    ]

  yes:
    ret i16 1

  no:
    ret i16 0
}

We currently get this result:

testbtst:                               ; @<!-- -->testbtst
; %bb.0:                                ; %entry
	move.l	%d0, %d1
	and.l	#<!-- -->65535, %d1
	sub.l	#<!-- -->11, %d1
	bhi	.LBB0_3
; %bb.1:                                ; %entry
	and.l	#<!-- -->65535, %d0
	move.l	#<!-- -->3612, %d1
	btst	%d0, %d1
	bne	.LBB0_3        ; &lt;------- Erroneous condition
; %bb.2:                                ; %yes
	moveq	#<!-- -->1, %d0
	rts
.LBB0_3:                                ; %no
	moveq	#<!-- -->0, %d0
	rts

The cause of this is a line that explicitly reverses the btst condition code. But on M68k, btst sets condition codes the same as and with a bitmask, meaning EQ indicates failure (bit is zero) and not success, so the condition does not need to be reversed.

In my testing, I've only been able to get switch statements to lower to btst, so I wasn't able to explicitly test other options for lowering. But (if possible to trigger) I believe they have the same logical error. For example, in LowerAndToBTST(), a comment specifies that it's lowering a case where the and result is compared against zero, which means the corresponding btst condition should also not be reversed.

This patch simply flips the ternary expression in getBitTestCondition() to match the ISD condition code with the same M68k code, instead of the opposite.

---

Full diff: https://github.com/llvm/llvm-project/pull/153086.diff

1 Files Affected:

• (modified) llvm/lib/Target/M68k/M68kISelLowering.cpp (+2-2)

diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 594ea9f48c201..cf666862b775d 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -1667,8 +1667,8 @@ static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
 
   SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
 
-  // NOTE BTST sets CCR.Z flag
-  M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
+  // NOTE BTST sets CCR.Z flag if bit is 0, same as AND with bitmask
+  M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_EQ : M68k::COND_NE;
   return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
                      DAG.getConstant(Cond, DL, MVT::i8), BTST);
 }

[dansalvato]

Requesting review from @mshockwave

[mshockwave]

Generally looks good. The key here is that BEQ branches when Z is one, therefore if we're comparing against zero in the setcc we should not flip the condition.
Could you add a codegen test?

[dansalvato]

I added a test that includes my example, and while doing that I also managed to get a second pattern to lower into BTST (AND with masked bit), so I included that test case as well. Both are branching correctly with this patch.

[mshockwave]

LGTM, thanks

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