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[PowerPC] Change half to use soft promotion rather than PromoteFloat #152632

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06e92fa
[SelectionDAG] Add `f16` soft promotion for `lrint` and `lround`
tgross35 Aug 8, 2025
43e0891
Do not commit: merge ppc soft promotion change with lrint fix
tgross35 Sep 10, 2025
a636c23
[PowerPC] Change `half` to use soft promotion rather than `PromoteFloat`
tgross35 Aug 6, 2025
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2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -113,6 +113,8 @@ Changes to the MIPS Backend
Changes to the PowerPC Backend
------------------------------

* `half` now uses a soft float ABI, which works correctly in more cases.

Changes to the RISC-V Backend
-----------------------------

Expand Down
15 changes: 13 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Expand Up @@ -20,6 +20,7 @@

#include "LegalizeTypes.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
Expand Down Expand Up @@ -3737,10 +3738,20 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
Res = SoftPromoteHalfOp_FAKE_USE(N, OpNo);
break;
case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::LLRINT:
case ISD::LLROUND:
case ISD::LRINT:
case ISD::LROUND:
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
case ISD::STRICT_LLRINT:
case ISD::STRICT_LLROUND:
case ISD::STRICT_LRINT:
case ISD::STRICT_LROUND:
Res = SoftPromoteHalfOp_FP_TO_XINT(N);
break;
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break;
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -790,6 +790,8 @@ namespace llvm {

bool useSoftFloat() const override;

bool softPromoteHalfType() const override { return true; }

bool hasSPE() const;

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/ARM/lrint-conv.ll
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@@ -1,12 +1,15 @@
; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP

; FIXME: crash
; define i32 @testmswh_builtin(half %x) {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
; SOFTFP-LABEL: testmswh_builtin:
; SOFTFP: bl lrintf
; HARDFP-LABEL: testmswh_builtin:
; HARDFP: bl lrintf
define i32 @testmswh_builtin(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}

; SOFTFP-LABEL: testmsws_builtin:
; SOFTFP: bl lrintf
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Generic/half.ll
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Expand Up @@ -29,9 +29,9 @@
; RUN: %if mips-registered-target %{ llc %s -o - -mtriple=mipsel-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if msp430-registered-target %{ llc %s -o - -mtriple=msp430-none-elf | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if nvptx-registered-target %{ llc %s -o - -mtriple=nvptx64-nvidia-cuda | FileCheck %s --check-prefixes=NOCRASH %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if riscv-registered-target %{ llc %s -o - -mtriple=riscv32-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if riscv-registered-target %{ llc %s -o - -mtriple=riscv64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if sparc-registered-target %{ llc %s -o - -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
Expand Down
33 changes: 24 additions & 9 deletions llvm/test/CodeGen/LoongArch/lrint-conv.ll
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Expand Up @@ -5,16 +5,31 @@
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I32
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I64

; FIXME: crash
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_lrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f16:
; LA32: bl lrintf
;
; LA64-I32-LABEL: test_lrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(lrintf)
;
; LA64-I64-LABEL: test_lrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(lrintf)
%res = tail call ITy @llvm.lrint.ITy.f16(half %x)
ret ITy %res
}

; define ITy @test_llrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_llrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_llrint_ixx_f16:
; LA32: bl llrintf
;
; LA64-I32-LABEL: test_llrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(llrintf)
;
; LA64-I64-LABEL: test_llrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(llrintf)
%res = tail call ITy @llvm.llrint.ITy.f16(half %x)
ret ITy %res
}

define ITy @test_lrint_ixx_f32(float %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f32:
Expand Down
23 changes: 11 additions & 12 deletions llvm/test/CodeGen/Mips/llrint-conv.ll
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@@ -1,19 +1,18 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/Mips/lrint-conv.ll
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@@ -1,19 +1,22 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
; CHECK-LABEL: testmswh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
; CHECK-LABEL: testmsxh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
62 changes: 5 additions & 57 deletions llvm/test/CodeGen/PowerPC/atomics.ll
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Expand Up @@ -469,39 +469,20 @@ define i64 @and_i64_release(ptr %mem, i64 %operand) {
define half @load_atomic_f16__seq_cst(ptr %ptr) {
; PPC32-LABEL: load_atomic_f16__seq_cst:
; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0
; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: sync
; PPC32-NEXT: lhz r3, 0(r3)
; PPC32-NEXT: cmpw cr7, r3, r3
; PPC32-NEXT: bne- cr7, .+4
; PPC32-NEXT: isync
; PPC32-NEXT: bl __extendhfsf2
; PPC32-NEXT: lwz r0, 20(r1)
; PPC32-NEXT: addi r1, r1, 16
; PPC32-NEXT: mtlr r0
; PPC32-NEXT: blr
;
; PPC64-LABEL: load_atomic_f16__seq_cst:
; PPC64: # %bb.0:
; PPC64-NEXT: mflr r0
; PPC64-NEXT: stdu r1, -112(r1)
; PPC64-NEXT: std r0, 128(r1)
; PPC64-NEXT: .cfi_def_cfa_offset 112
; PPC64-NEXT: .cfi_offset lr, 16
; PPC64-NEXT: sync
; PPC64-NEXT: lhz r3, 0(r3)
; PPC64-NEXT: cmpd cr7, r3, r3
; PPC64-NEXT: bne- cr7, .+4
; PPC64-NEXT: isync
; PPC64-NEXT: bl __extendhfsf2
; PPC64-NEXT: nop
; PPC64-NEXT: addi r1, r1, 112
; PPC64-NEXT: ld r0, 16(r1)
; PPC64-NEXT: mtlr r0
; PPC64-NEXT: blr
%val = load atomic half, ptr %ptr seq_cst, align 2
ret half %val
Expand Down Expand Up @@ -575,44 +556,11 @@ define double @load_atomic_f64__seq_cst(ptr %ptr) {
}

define void @store_atomic_f16__seq_cst(ptr %ptr, half %val1) {
; PPC32-LABEL: store_atomic_f16__seq_cst:
; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0
; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: .cfi_offset r30, -8
; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill
; PPC32-NEXT: mr r30, r3
; PPC32-NEXT: bl __truncsfhf2
; PPC32-NEXT: sync
; PPC32-NEXT: sth r3, 0(r30)
; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload
; PPC32-NEXT: lwz r0, 20(r1)
; PPC32-NEXT: addi r1, r1, 16
; PPC32-NEXT: mtlr r0
; PPC32-NEXT: blr
;
; PPC64-LABEL: store_atomic_f16__seq_cst:
; PPC64: # %bb.0:
; PPC64-NEXT: mflr r0
; PPC64-NEXT: stdu r1, -128(r1)
; PPC64-NEXT: std r0, 144(r1)
; PPC64-NEXT: .cfi_def_cfa_offset 128
; PPC64-NEXT: .cfi_offset lr, 16
; PPC64-NEXT: .cfi_offset r30, -16
; PPC64-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; PPC64-NEXT: mr r30, r3
; PPC64-NEXT: bl __truncsfhf2
; PPC64-NEXT: nop
; PPC64-NEXT: sync
; PPC64-NEXT: sth r3, 0(r30)
; PPC64-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
; PPC64-NEXT: addi r1, r1, 128
; PPC64-NEXT: ld r0, 16(r1)
; PPC64-NEXT: mtlr r0
; PPC64-NEXT: blr
; CHECK-LABEL: store_atomic_f16__seq_cst:
; CHECK: # %bb.0:
; CHECK-NEXT: sync
; CHECK-NEXT: sth r4, 0(r3)
; CHECK-NEXT: blr
store atomic half %val1, ptr %ptr seq_cst, align 2
ret void
}
Expand Down
13 changes: 6 additions & 7 deletions llvm/test/CodeGen/PowerPC/f128-conv.ll
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Expand Up @@ -1349,9 +1349,6 @@ define half @trunc(fp128 %a) nounwind {
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: bl __trunckfhf2
; CHECK-NEXT: nop
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
Expand All @@ -1364,9 +1361,6 @@ define half @trunc(fp128 %a) nounwind {
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: bl __trunckfhf2
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: bl __extendhfsf2
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
Expand All @@ -1379,15 +1373,20 @@ entry:
define fp128 @ext(half %a) nounwind {
; CHECK-LABEL: ext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp v2, f0
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ext:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: bl __extendhfsf2
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
Expand Down
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