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Merged
merged 6 commits into from
Oct 12, 2025
Merged

[X86][GlobalISel] Improve carry value selection #146586

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dbece84
[X86][GlobalISel] Improve carry value selection
e-kud Jul 1, 2025
b9517ee
Merge remote-tracking branch 'origin/main' into global-carry-value
e-kud Jul 29, 2025
5ca565c
Always store a carry bit in a GPR
e-kud Jul 29, 2025
a89f6af
Some names for the test
e-kud Jul 29, 2025
ed72606
Format
e-kud Jul 29, 2025
5d1af70
Merge branch 'main' into global-carry-value
e-kud Oct 12, 2025
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47 changes: 33 additions & 14 deletions llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1163,14 +1163,13 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
I.getOpcode() == TargetOpcode::G_USUBO) &&
"unexpected instruction");

const Register DstReg = I.getOperand(0).getReg();
const Register CarryOutReg = I.getOperand(1).getReg();
const Register Op0Reg = I.getOperand(2).getReg();
const Register Op1Reg = I.getOperand(3).getReg();
bool IsSub = I.getOpcode() == TargetOpcode::G_USUBE ||
I.getOpcode() == TargetOpcode::G_USUBO;
bool HasCarryIn = I.getOpcode() == TargetOpcode::G_UADDE ||
I.getOpcode() == TargetOpcode::G_USUBE;
auto &CarryMI = cast<GAddSubCarryOut>(I);

const Register DstReg = CarryMI.getDstReg();
const Register CarryOutReg = CarryMI.getCarryOutReg();
const Register Op0Reg = CarryMI.getLHSReg();
const Register Op1Reg = CarryMI.getRHSReg();
bool IsSub = CarryMI.isSub();

const LLT DstTy = MRI.getType(DstReg);
assert(DstTy.isScalar() && "selectUAddSub only supported for scalar types");
Expand Down Expand Up @@ -1206,14 +1205,15 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
llvm_unreachable("selectUAddSub unsupported type.");
}

const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
const RegisterBank &CarryRB = *RBI.getRegBank(CarryOutReg, MRI, TRI);
const TargetRegisterClass *CarryRC =
getRegClass(MRI.getType(CarryOutReg), CarryRB);

unsigned Opcode = IsSub ? OpSUB : OpADD;

// G_UADDE/G_USUBE - find CarryIn def instruction.
if (HasCarryIn) {
Register CarryInReg = I.getOperand(4).getReg();
if (auto CarryInMI = dyn_cast<GAddSubCarryInOut>(&I)) {
Register CarryInReg = CarryInMI->getCarryInReg();
MachineInstr *Def = MRI.getVRegDef(CarryInReg);
while (Def->getOpcode() == TargetOpcode::G_TRUNC) {
CarryInReg = Def->getOperand(1).getReg();
Expand All @@ -1230,7 +1230,7 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
X86::EFLAGS)
.addReg(CarryInReg);

if (!RBI.constrainGenericRegister(CarryInReg, *DstRC, MRI))
if (!RBI.constrainGenericRegister(CarryInReg, *CarryRC, MRI))
return false;

Opcode = IsSub ? OpSBB : OpADC;
Expand All @@ -1253,9 +1253,28 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
.addReg(X86::EFLAGS);

if (!constrainSelectedInstRegOperands(Inst, TII, TRI, RBI) ||
!RBI.constrainGenericRegister(CarryOutReg, *DstRC, MRI))
!RBI.constrainGenericRegister(CarryOutReg, *CarryRC, MRI))
return false;

// If there are instructions that use carry as value, we need to lower it
// differently than setting EFLAGS
Register SetCarryCC;
for (auto &Use :
llvm::make_early_inc_range(MRI.use_nodbg_operands(CarryOutReg))) {
MachineInstr *MI = Use.getParent();
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@arsenm arsenm Jul 2, 2025

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Doing a use scan during selection seems like a really bad idea. Shouldn't touch anything other than the current instruction

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@e-kud e-kud Jul 29, 2025

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Yeah, so it looks like if we meet operations with carry bits in the selector we have to lower a carry bit into GPR. Otherwise it should be lowered into target opcodes by combiners.

if (MI->isCopy() && MI->getOperand(0).getReg() == X86::EFLAGS)
continue;
if (!SetCarryCC) {
SetCarryCC = MRI.createGenericVirtualRegister(MRI.getType(CarryOutReg));
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr),
SetCarryCC)
.addImm(X86::COND_B);
if (!RBI.constrainGenericRegister(SetCarryCC, *CarryRC, MRI))
return false;
}
Use.setReg(SetCarryCC);
}

I.eraseFromParent();
return true;
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -164,11 +164,11 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.scalarize(0);

getActionDefinitionsBuilder({G_UADDE, G_UADDO, G_USUBE, G_USUBO})
.legalFor({{s8, s1}, {s16, s1}, {s32, s1}})
.legalFor(Is64Bit, {{s64, s1}})
.legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
.legalFor(Is64Bit, {{s64, s8}})
.widenScalarToNextPow2(0, /*Min=*/32)
.clampScalar(0, s8, sMaxScalar)
.clampScalar(1, s1, s1)
.clampScalar(1, s8, s8)
.scalarize(0);

// integer multiply
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -157,8 +157,8 @@ body: |
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
Expand Down Expand Up @@ -192,8 +192,8 @@ body: |
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
Expand All @@ -219,8 +219,8 @@ body: |
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)
; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)
; X64-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
; X64-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X64-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV2]]
; X64-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; X64-NEXT: $rax = COPY [[UADDO]](s64)
; X64-NEXT: $rdx = COPY [[UADDE]](s64)
; X64-NEXT: RET 0
Expand All @@ -230,10 +230,10 @@ body: |
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV4]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s8) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s8) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE2]](s32), [[UADDE4]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
Expand Down
15 changes: 10 additions & 5 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ body: |
; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CTLZ]], [[C1]]
; X64-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C]]
; X64-NEXT: RET 0, implicit [[AND1]](s64)
;
; X86-LABEL: name: test_ctlz35
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[TRUNC:%[0-9]+]]:_(s35) = G_TRUNC [[COPY]](s64)
Expand All @@ -46,12 +47,15 @@ body: |
; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C]](s32)
; X86-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; X86-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV1]](s64)
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[UV8]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[UV9]], [[USUBO1]]
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV6]], [[UV8]]
; X86-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[USUBO1]](s8)
; X86-NEXT: [[ZEXT2:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV7]], [[UV9]], [[ZEXT2]]
; X86-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[USUBE1]](s8)
; X86-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; X86-NEXT: [[TRUNC1:%[0-9]+]]:_(s35) = G_TRUNC [[MV2]](s64)
; X86-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s35)
; X86-NEXT: RET 0, implicit [[ZEXT2]](s64)
; X86-NEXT: [[TRUNC3:%[0-9]+]]:_(s35) = G_TRUNC [[MV2]](s64)
; X86-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC3]](s35)
; X86-NEXT: RET 0, implicit [[ZEXT3]](s64)
%0(s64) = COPY $rdx
%1:_(s35) = G_TRUNC %0(s64)
%2:_(s35) = G_CTLZ %1
Expand Down Expand Up @@ -97,6 +101,7 @@ body: |
; X64-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[DEF]](s64)
; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTLZ]](s64)
; X64-NEXT: RET 0, implicit [[COPY]](s64)
;
; X86-LABEL: name: test_ctlz64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -157,8 +157,8 @@ body: |
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
Expand Down Expand Up @@ -192,8 +192,8 @@ body: |
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
Expand All @@ -219,8 +219,8 @@ body: |
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)
; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)
; X64-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
; X64-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X64-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]
; X64-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; X64-NEXT: $rax = COPY [[USUBO]](s64)
; X64-NEXT: $rdx = COPY [[USUBE]](s64)
; X64-NEXT: RET 0
Expand All @@ -230,10 +230,10 @@ body: |
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV4]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]
; X86-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]
; X86-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV4]]
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]
; X86-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s8) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]
; X86-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s8) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBE2]](s32), [[USUBE4]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@ body: |
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
Expand Down Expand Up @@ -97,8 +97,8 @@ body: |
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
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Expand Up @@ -32,8 +32,8 @@ body: |
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
Expand Down Expand Up @@ -99,8 +99,8 @@ body: |
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
; X86-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[UV1]](s32)
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
Expand Down
26 changes: 23 additions & 3 deletions llvm/test/CodeGen/X86/pr49087.ll → llvm/test/CodeGen/X86/GlobalISel/pr49087.ll
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@@ -1,9 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -global-isel < %s 2>&1 | FileCheck %s
; REQUIRES: asserts
; XFAIL: *

define i32 @test_01(ptr %p, i64 %len, i32 %x) {
; CHECK-LABEL: test_01
; CHECK-LABEL: test_01:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: subq %rax, %rsi
; CHECK-NEXT: setb %cl
; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: # %bb.2: # %backedge
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: imulq $4, %rsi, %rcx
; CHECK-NEXT: addq %rdi, %rcx
; CHECK-NEXT: cmpl %edx, (%rcx)
; CHECK-NEXT: sete %cl
; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.3: # %failure
; CHECK-NEXT: .LBB0_4: # %exit
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: retq

entry:
%scevgep = getelementptr i32, ptr %p, i64 -1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ body: |
bb.0 (%ir-block.0):
%0(s32) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(s1) = IMPLICIT_DEF
%3(s32), %4(s1) = G_UADDE %0, %1, %2
%2(s8) = IMPLICIT_DEF
%3(s32), %4(s8) = G_UADDE %0, %1, %2
RET 0

...
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir
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Expand Up @@ -31,10 +31,10 @@ body: |
; X32: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X32: [[DEF3:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X32: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[DEF]], [[DEF2]], implicit-def $eflags
; X32: [[COPY:%[0-9]+]]:gr32 = COPY $eflags
; X32: [[COPY:%[0-9]+]]:gr8 = COPY $eflags
; X32: $eflags = COPY [[COPY]]
; X32: [[ADC32rr:%[0-9]+]]:gr32 = ADC32rr [[DEF1]], [[DEF3]], implicit-def $eflags, implicit $eflags
; X32: [[COPY1:%[0-9]+]]:gr32 = COPY $eflags
; X32: [[COPY1:%[0-9]+]]:gr8 = COPY $eflags
; X32: $eax = COPY [[ADD32rr]]
; X32: $edx = COPY [[ADC32rr]]
; X32: RET 0, implicit $eax, implicit $edx
Expand All @@ -43,9 +43,8 @@ body: |
%2(s32) = IMPLICIT_DEF
%3(s32) = IMPLICIT_DEF
%9(s8) = G_CONSTANT i8 0
%4(s1) = G_TRUNC %9(s8)
%5(s32), %6(s1) = G_UADDE %0, %2, %4
%7(s32), %8(s1) = G_UADDE %1, %3, %6
%5(s32), %6(s8) = G_UADDE %0, %2, %9
%7(s32), %8(s8) = G_UADDE %1, %3, %6
$eax = COPY %5(s32)
$edx = COPY %7(s32)
RET 0, implicit $eax, implicit $edx
Expand Down
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