[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs #132704

mgoudar · 2025-03-24T10:14:36Z

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor.

i6400 and i6500 share same instruction latencies.

CPU has following pipelines

Two ALUs
Multiply and Divide unit (MDU)
Branch Unit (CTU)
Load/Store Unit (LSU)
Short Floating-point Unit and
Long Floating-point Unit

Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

djtodoro · 2025-03-24T10:19:11Z

Thanks for working on this! Can you please share a document that shows the instruction latencies?

llvm/lib/Target/Mips/Mips32r6InstrInfo.td

llvm/lib/Target/Mips/MipsScheduleI6400.td

mshockwave · 2025-03-24T17:17:02Z

llvm/lib/Target/Mips/MipsScheduleI6400.td

+
+  // LSU pipelines
+  // =============
+  def : InstRW<[I6400WriteLSUStore], (instrs SB, SD, SH, SW, SDC1, SDC164, SWC1, SWC2_R6,


Is it possible avoid using SchedWriteRes + InstRW and using the normal SchedWrite + WriteRes instead?

InstRW really should be used for "ad-hoc fixing" nowadays (e.g. instruction A & B share the same scheduling class in their instruction definitions, but they should be in two different scheduling classes in your core)

llvm/lib/Target/Mips/MipsScheduleI6400.td

llvm/test/tools/llvm-mca/Mips/i6400.s

mgoudar · 2025-03-25T06:42:43Z

Thanks for working on this! Can you please share a document that shows the instruction latencies?

Hi, please find the instruction latency at public document: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

llvm/lib/Target/Mips/MipsScheduleI6400.td

llvm/lib/Target/Mips/Mips32r6InstrInfo.td

mshockwave · 2025-03-27T20:53:54Z

llvm/test/tools/llvm-mca/Mips/i6400.s

+	mul	$3, $2, $3
+	sw	$3, 8($sp)
+	div	$2, $1
+	sw	$2, 0($sp)


Could you add more tests on simple integer and floating point arithmetics instructions, as well as some vector instructions (they're called MSA?).

yes. I will add. thank you for the review

I have extended the existing test to cover more instructions.

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit

i6400 and i6500 are in-order cores. hence set BufferSize and MicroBufferSize to 0

- remove hasNoSchedulingInfo in Mips32r6InstrInfo.td - define BufferSize to 0 for all resources - remove timeline test in llvm-mca testcase

Extend i64..s to cover more instructions including MSA

mshockwave · 2025-04-04T21:12:12Z

llvm/test/tools/llvm-mca/Mips/i6400.s

@@ -0,0 +1,133 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -timeline -iterations=1 < %s | FileCheck %s


when I suggested to remove -timeline for scheduling model test, I meant remove this flag from the RUN line and run update_mca_test_checks.py again to update the test (rather than manually remove the related CHECKs)

thank you for pointing me the process. I have now removed --timeline option and rerun with update_mca_test_checks.py

mshockwave · 2025-04-04T21:16:23Z

llvm/test/tools/llvm-mca/Mips/i6400.s

@@ -0,0 +1,133 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -timeline -iterations=1 < %s | FileCheck %s


I just checked the processor definitions: please correct me if I'm wrong, but it seems like none of the in-tree MIPS processors support MSA, then why did you want to assign meaningful latency/occupancy to those instructions?

i6400 and i6500 comes with MSA implemented and enabled by default, user can disable MSA with reset bit from the software. I think I need to enable FeatureMSA as part of i6400/i6500 cpu definition. I have created a separate PR: #134985

removed --timeline option from the RUN command

mshockwave

Personally I'm not really a fan of using InstRW as I pointed out in one of my comments. But I guess it's up to MIPS maintainers to make the call on that. Other than that, LGTM.
@djtodoro do you have any other comments?

djtodoro

Lets try to avoid InstRW.

mgoudar · 2025-04-28T16:10:35Z

Lets try to avoid InstRW.

Hi, thank you for the review and the feedback. We have started porting work. We will port all existing scheduling model for MIPS cpus to new scheduling API soon.

djtodoro · 2025-04-28T18:35:47Z

OK, it can be addressed as a separate PR, but please handle all MIPS CPUs that use InstRW. Thanks!

mgoudar · 2025-04-29T05:43:22Z

OK, it can be addressed as a separate PR, but please handle all MIPS CPUs that use InstRW. Thanks!

yes sure. thank you.

llvm-ci · 2025-04-29T07:45:16Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-sie-ubuntu-fast running on sie-linux-worker while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/144/builds/23854

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: tools/llvm-mca/Mips/i6400.s' FAILED ********************
Exit Code: 2

Command Output (stderr):
--
/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -iterations=1 < /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s | /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s # RUN: at line 2
+ /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -iterations=1
+ /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s
/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/llvm-mca: unable to get target for 'mips64el', see --version and --triple.FileCheck error: '<stdin>' is empty.
FileCheck command line:  /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s

--

********************

llvm-ci · 2025-04-29T07:56:36Z

LLVM Buildbot has detected a new failure on builder llvm-nvptx-nvidia-win running on as-builder-8 while building llvm at step 7 "test-build-unified-tree-check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/54/builds/8671

Here is the relevant piece of the build log for the reference

Step 7 (test-build-unified-tree-check-llvm) failure: test (failure)
******************** TEST 'LLVM :: tools/llvm-mca/Mips/i6400.s' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
c:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\bin\llvm-mca.exe -mtriple=mips64el -mcpu=i6400 --mattr=msa -iterations=1 < C:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\llvm-project\llvm\test\tools\llvm-mca\Mips\i6400.s | c:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\bin\filecheck.exe C:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\llvm-project\llvm\test\tools\llvm-mca\Mips\i6400.s
# executed command: 'c:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\bin\llvm-mca.exe' -mtriple=mips64el -mcpu=i6400 --mattr=msa -iterations=1
# .---command stderr------------
# | c:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\bin\llvm-mca.exe: unable to get target for 'mips64el', see --version and --triple.
# `-----------------------------
# error: command failed with exit status: 1
# executed command: 'c:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\bin\filecheck.exe' 'C:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\llvm-project\llvm\test\tools\llvm-mca\Mips\i6400.s'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  c:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\build\bin\filecheck.exe C:\buildbot\as-builder-8\llvm-nvptx-nvidia-win\llvm-project\llvm\test\tools\llvm-mca\Mips\i6400.s
# `-----------------------------
# error: command failed with exit status: 2

--

********************

…vm#132704)" This reverts commit ffcca51.

…32704)" (#137767) This reverts commit ffcca51.

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

…vm#132704)" (llvm#137767) This reverts commit ffcca51.

mshockwave · 2025-04-29T17:18:32Z

LLVM Buildbot has detected a new failure on builder llvm-nvptx-nvidia-win running on as-builder-8 while building llvm at step 7 "test-build-unified-tree-check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/54/builds/8671

Here is the relevant piece of the build log for the reference

You forgot to add lit.local.cfg like this: https://github.com/llvm/llvm-project/blob/main/llvm/test/tools/llvm-mca/RISCV/lit.local.cfg
Which limits the tests to LLVM that has the MIPS backend (or you can add REQUIRES: mips-registered-target to every single tests under the Mips folder, but usually people prefer lit.local.cfg)

mgoudar · 2025-04-30T04:55:28Z

LLVM Buildbot has detected a new failure on builder llvm-nvptx-nvidia-win running on as-builder-8 while building llvm at step 7 "test-build-unified-tree-check-llvm".
Full details are available at: https://lab.llvm.org/buildbot/#/builders/54/builds/8671
Here is the relevant piece of the build log for the reference

You forgot to add lit.local.cfg like this: https://github.com/llvm/llvm-project/blob/main/llvm/test/tools/llvm-mca/RISCV/lit.local.cfg Which limits the tests to LLVM that has the MIPS backend (or you can add REQUIRES: mips-registered-target to every single tests under the Mips folder, but usually people prefer lit.local.cfg)

Thank you. I will add lit.local.cfg and create new pr. thanks for your feedback.

…2704) Relands llvm#132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

#137984) Relands #132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

llvm-ci · 2025-05-06T06:47:04Z

LLVM Buildbot has detected a new failure on builder llvm-nvptx-nvidia-ubuntu running on as-builder-7 while building llvm at step 6 "test-build-unified-tree-check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/180/builds/17043

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-llvm) failure: test (failure)
******************** TEST 'LLVM :: tools/llvm-mca/Mips/i6400.s' FAILED ********************
Exit Code: 2

Command Output (stderr):
--
/home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/build/bin/llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -iterations=1 < /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s | /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/build/bin/FileCheck /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s # RUN: at line 2
+ /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/build/bin/llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -iterations=1
+ /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/build/bin/FileCheck /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s
/home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/build/bin/llvm-mca: unable to get target for 'mips64el', see --version and --triple.FileCheck error: '<stdin>' is empty.
FileCheck command line:  /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/build/bin/FileCheck /home/buildbot/worker/as-builder-7/ramdisk/llvm-nvptx-nvidia-ubuntu/llvm-project/llvm/test/tools/llvm-mca/Mips/i6400.s

--

********************

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

…vm#132704)" (llvm#137767) This reverts commit ffcca51.

…2704) (llvm#137984) Relands llvm#132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

…vm#132704)" (llvm#137767) This reverts commit ffcca51.

…2704) (llvm#137984) Relands llvm#132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

…vm#132704)" (llvm#137767) This reverts commit ffcca51.

…2704) (llvm#137984) Relands llvm#132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

…vm#132704)" (llvm#137767) This reverts commit ffcca51.

…2704) (llvm#137984) Relands llvm#132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

…vm#132704)" (llvm#137767) This reverts commit ffcca51.

djtodoro self-requested a review March 24, 2025 10:16

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mgoudar force-pushed the pr/add-mips-i6500-sched-model branch from d22c99a to e1a086e Compare March 26, 2025 09:41

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llvm/lib/Target/Mips/MipsScheduleI6400.td Outdated Show resolved Hide resolved

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mgoudar requested a review from mshockwave March 27, 2025 07:23

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mgoudar added 3 commits March 31, 2025 14:51

Set MicroOpBufferSize and BufferSize to 0

fc23bdf

i6400 and i6500 are in-order cores. hence set BufferSize and MicroBufferSize to 0

Address review comments

6784668

- remove hasNoSchedulingInfo in Mips32r6InstrInfo.td - define BufferSize to 0 for all resources - remove timeline test in llvm-mca testcase

mgoudar force-pushed the pr/add-mips-i6500-sched-model branch from b9b1cf4 to 6784668 Compare March 31, 2025 09:22

Cover more instructions in llvm-mca test

59e72f4

Extend i64..s to cover more instructions including MSA

mgoudar requested a review from mshockwave April 4, 2025 09:54

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Update llvm-mca test and rerun update_mca_test_checks.py

bb2188a

removed --timeline option from the RUN command

mgoudar requested a review from mshockwave April 9, 2025 05:58

mshockwave approved these changes Apr 9, 2025

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djtodoro requested changes Apr 9, 2025

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djtodoro approved these changes Apr 28, 2025

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brad0 merged commit ffcca51 into llvm:main Apr 29, 2025
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brad0 added a commit to brad0/llvm-project that referenced this pull request Apr 29, 2025

Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" This reverts commit ffcca51.

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (#1…

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…32704)" (#137767) This reverts commit ffcca51.

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" (llvm#137767) This reverts commit ffcca51.

mgoudar mentioned this pull request Apr 30, 2025

[MIPS] Reland Scheduling model for MIPS i6400 and i6500 CPUs (#132704) #137984

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" (llvm#137767) This reverts commit ffcca51.

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" (llvm#137767) This reverts commit ffcca51.

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" (llvm#137767) This reverts commit ffcca51.

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" (llvm#137767) This reverts commit ffcca51.

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Revert "[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (ll…

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…vm#132704)" (llvm#137767) This reverts commit ffcca51.

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		@@ -0,0 +1,133 @@
		# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
		# RUN: llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -timeline -iterations=1 < %s \| FileCheck %s

[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs #132704

[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs #132704

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