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AMDGPU: Replace ptr addrspace(1) undefs with poison #130900

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Merged
merged 1 commit into from
Mar 13, 2025
Merged

AMDGPU: Replace ptr addrspace(1) undefs with poison #130900

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,6 @@
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD
define amdgpu_kernel void @addi32(i32 %arg1, i32 %arg2) {
%res = add i32 %arg1, %arg2
store i32 %res, ptr addrspace(1) undef
store i32 %res, ptr addrspace(1) poison
ret void
}
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -102,11 +102,11 @@ entry:
br i1 %trunc, label %bb0, label %bb1

bb0:
store volatile i32 0, ptr addrspace(1) undef
store volatile i32 0, ptr addrspace(1) poison
unreachable

bb1:
store volatile i32 1, ptr addrspace(1) undef
store volatile i32 1, ptr addrspace(1) poison
unreachable
}

Expand Down Expand Up @@ -153,10 +153,10 @@ entry:
br i1 %and, label %bb0, label %bb1

bb0:
store volatile i32 0, ptr addrspace(1) undef
store volatile i32 0, ptr addrspace(1) poison
unreachable

bb1:
store volatile i32 1, ptr addrspace(1) undef
store volatile i32 1, ptr addrspace(1) poison
unreachable
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
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Expand Up @@ -96,7 +96,7 @@ define float @v_uitofp_to_f32_multi_use_lshr8_mask255(i32 %arg0) nounwind {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
%lshr.8 = lshr i32 %arg0, 8
store i32 %lshr.8, ptr addrspace(1) undef
store i32 %lshr.8, ptr addrspace(1) poison
%masked = and i32 %lshr.8, 255
%cvt = uitofp i32 %masked to float
ret float %cvt
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
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Expand Up @@ -22,7 +22,7 @@ entry:
br i1 %c, label %if.true, label %endif

if.true:
%val = load volatile i32, ptr addrspace(1) undef
%val = load volatile i32, ptr addrspace(1) poison
br label %endif

endif:
Expand Down Expand Up @@ -53,7 +53,7 @@ endif:
ret i32 %v

if.true:
%val = load volatile i32, ptr addrspace(1) undef
%val = load volatile i32, ptr addrspace(1) poison
br label %endif
}

Expand All @@ -78,7 +78,7 @@ entry:
br i1 %c, label %if.true, label %endif

if.true:
%val = load volatile i32, ptr addrspace(1) undef
%val = load volatile i32, ptr addrspace(1) poison
br label %endif

endif:
Expand Down Expand Up @@ -110,7 +110,7 @@ entry:
br i1 %c, label %if.true, label %endif

if.true:
%val = load volatile i32, ptr addrspace(1) undef
%val = load volatile i32, ptr addrspace(1) poison
br label %endif

endif:
Expand Down Expand Up @@ -237,7 +237,7 @@ bb1:
br i1 %cmp0, label %bb4, label %bb9

bb4:
%load = load volatile i32, ptr addrspace(1) undef, align 4
%load = load volatile i32, ptr addrspace(1) poison, align 4
%cmp1 = icmp slt i32 %tmp, %load
br i1 %cmp1, label %bb1, label %bb9

Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
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Expand Up @@ -483,7 +483,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
; GFX11-NEXT: s_endpgm
entry:
%ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel
store i64 %ext, ptr addrspace(1) undef
store i64 %ext, ptr addrspace(1) poison
ret void
}

Expand Down Expand Up @@ -628,7 +628,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_v(<8 x i64> inreg %vec, i32 %sel) {
; GFX11-NEXT: s_endpgm
entry:
%ext = extractelement <8 x i64> %vec, i32 %sel
store i64 %ext, ptr addrspace(1) undef
store i64 %ext, ptr addrspace(1) poison
ret void
}

Expand Down Expand Up @@ -744,7 +744,7 @@ define amdgpu_ps void @dyn_extract_v8i64_v_s(<8 x i64> %vec, i32 inreg %sel) {
; GFX11-NEXT: s_endpgm
entry:
%ext = extractelement <8 x i64> %vec, i32 %sel
store i64 %ext, ptr addrspace(1) undef
store i64 %ext, ptr addrspace(1) poison
ret void
}

Expand Down Expand Up @@ -849,7 +849,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se
; GFX11-NEXT: s_endpgm
entry:
%ext = extractelement <8 x i64> %vec, i32 %sel
store i64 %ext, ptr addrspace(1) undef
store i64 %ext, ptr addrspace(1) poison
ret void
}

Expand Down Expand Up @@ -1800,7 +1800,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i
; GFX11-NEXT: s_endpgm
entry:
%ext = extractelement <8 x ptr addrspace(1)> %vec, i32 %idx
store ptr addrspace(1) %ext, ptr addrspace(1) undef
store ptr addrspace(1) %ext, ptr addrspace(1) poison
ret void
}

Expand Down
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