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[LV] Don't skip instrs with side-effects in reg pressure computation. #126415

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Mar 19, 2025
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[LV] Don't skip instrs with side-effects in reg pressure computation. #126415

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[LV] Don't skip instrs with side-effects in reg pressure computation.
fhahn Feb 9, 2025
c58a2e6
!fixup extend comment
fhahn Mar 19, 2025
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5 changes: 3 additions & 2 deletions llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
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Expand Up @@ -5270,8 +5270,9 @@ LoopVectorizationCostModel::calculateRegisterUsage(ArrayRef<ElementCount> VFs) {
for (Instruction *ToRemove : List)
OpenIntervals.erase(ToRemove);

// Ignore instructions that are never used within the loop.
if (!Ends.count(I))
// Ignore instructions that are never used within the loop and do not have
// side-effects.
if (!Ends.count(I) && !I->mayHaveSideEffects())
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I guess this may also include calls to intrinsics or functions that return void?

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Yes, any instruction that is not explicitly used and has side-effects. So here we don't skip intrinsics any more or calls that return void.

Instructions that should not count as 'real' users, e.g. llvm.assume() calls are skipped below (via ValuesToIgnore).

continue;

// Skip ignored values.
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3 changes: 2 additions & 1 deletion llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
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Expand Up @@ -15,8 +15,9 @@
define void @get_invariant_reg_usage(ptr %z) {
; CHECK-LABEL: LV: Checking a loop in 'get_invariant_reg_usage'
; CHECK: LV(REG): VF = vscale x 16
; CHECK-NEXT: LV(REG): Found max usage: 1 item
; CHECK-NEXT: LV(REG): Found max usage: 2 item
; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 3 registers
; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 1 registers
; CHECK-NEXT: LV(REG): Found invariant usage: 2 item
; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers
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3 changes: 2 additions & 1 deletion llvm/test/Transforms/LoopVectorize/LoongArch/reg-usage.ll
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Expand Up @@ -15,8 +15,9 @@ define void @bar(ptr %A, i32 signext %n) {
; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
; CHECK-SCALAR-NEXT: LV: The target has 30 registers of LoongArch::GPRRC register class
; CHECK-SCALAR-NEXT: LV: The target has 32 registers of LoongArch::FPRRC register class
; CHECK-VECTOR: LV(REG): Found max usage: 1 item
; CHECK-VECTOR: LV(REG): Found max usage: 2 item
; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::VRRC, 3 registers
; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
; CHECK-VECTOR-NEXT: LV(REG): Found invariant usage: 1 item
; CHECK-VECTOR-NEXT: LV(REG): RegisterClass: LoongArch::GPRRC, 1 registers
; CHECK-VECTOR-NEXT: LV: The target has 32 registers of LoongArch::VRRC register class
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4 changes: 2 additions & 2 deletions llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
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Expand Up @@ -179,7 +179,7 @@ define void @double_(ptr nocapture %A, i32 %n) nounwind uwtable ssp {

;CHECK-PWR9: LV(REG): VF = 1
;CHECK-PWR9: LV(REG): Found max usage: 2 item
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 3 registers
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
;CHECK-PWR9: LV(REG): Found invariant usage: 1 item
;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
Expand Down Expand Up @@ -248,7 +248,7 @@ define void @fp16_(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRow
;CHECK-LABEL: fp16_
;CHECK: LV(REG): VF = 1
;CHECK: LV(REG): Found max usage: 2 item
;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 4 registers
;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 5 registers
;CHECK: LV(REG): RegisterClass: PPC::VSXRC, 2 registers
entry:
%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
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10 changes: 6 additions & 4 deletions llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
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Expand Up @@ -128,8 +128,9 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; CHECK-NEXT: LV(REG): At #5 Interval # 3
; CHECK-NEXT: LV(REG): At #6 Interval # 3
; CHECK-NEXT: LV(REG): At #7 Interval # 3
; CHECK-NEXT: LV(REG): At #9 Interval # 1
; CHECK-NEXT: LV(REG): At #10 Interval # 2
; CHECK-NEXT: LV(REG): At #8 Interval # 3
; CHECK-NEXT: LV(REG): At #9 Interval # 2
; CHECK-NEXT: LV(REG): At #10 Interval # 3
; CHECK-NEXT: LV(REG): VF = vscale x 4
; CHECK-NEXT: LV(REG): Found max usage: 2 item
; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
Expand Down Expand Up @@ -377,8 +378,9 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; CHECK-NEXT: LV(REG): At #5 Interval # 3
; CHECK-NEXT: LV(REG): At #6 Interval # 3
; CHECK-NEXT: LV(REG): At #7 Interval # 3
; CHECK-NEXT: LV(REG): At #9 Interval # 1
; CHECK-NEXT: LV(REG): At #10 Interval # 2
; CHECK-NEXT: LV(REG): At #8 Interval # 3
; CHECK-NEXT: LV(REG): At #9 Interval # 2
; CHECK-NEXT: LV(REG): At #10 Interval # 3
; CHECK-NEXT: LV(REG): VF = vscale x 4
; CHECK-NEXT: LV(REG): Found max usage: 2 item
; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
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