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[WIP][AMDGPU] Change CC_AMDGPU_Func to only use SGPR0 to SGPR27 for inreg argument passing #115753

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[WIP][AMDGPU] Change CC_AMDGPU_Func to only use SGPR0 to SGPR27 for inreg argument passing #115753

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4 changes: 2 additions & 2 deletions llvm/docs/AMDGPUUsage.rst
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Expand Up @@ -16545,7 +16545,7 @@ On entry to a function:
:ref:`amdgpu-amdhsa-kernel-prolog-m0`.
4. The EXEC register is set to the lanes active on entry to the function.
5. MODE register: *TBD*
6. VGPR0-31 and SGPR4-29 are used to pass function input arguments as described
6. VGPR0-31 and SGPR4-27 are used to pass function input arguments as described
below.
7. SGPR30-31 return address (RA). The code address that the function must
return to when it completes. The value is undefined if the function is *no
Expand Down Expand Up @@ -16796,7 +16796,7 @@ The input and result arguments are assigned in order in the following manner:
How are overly aligned structures allocated on the stack?

* SGPR arguments are assigned to consecutive SGPRs starting at SGPR0 up to
SGPR29.
SGPR27.

If there are more arguments than will fit in these registers, the remaining
arguments are allocated on the stack in order on naturally aligned
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
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Expand Up @@ -127,7 +127,7 @@ def CC_AMDGPU_Func : CallingConv<[
CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,

CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
!foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
!foreach(i, !range(0, 28), !cast<Register>("SGPR"#i)) // SGPR0-27
>>>,

CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<
Expand Down