[AMDGPU] Make __GCC_DESTRUCTIVE_SIZE 128 on AMDGPU
#115241
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@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-backend-amdgpu Author: Joseph Huber (jhuber6) ChangesSummary: Full diff: https://github.com/llvm/llvm-project/pull/115241.diff 1 Files Affected:
diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h
index 6edd3474d4edae..81e96ed65c47bf 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -462,6 +462,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
}
bool hasHIPImageSupport() const override { return HasImage; }
+
+ std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+ return std::make_pair(128, 128);
+ }
};
} // namespace targets
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@llvm/pr-subscribers-clang Author: Joseph Huber (jhuber6) ChangesSummary: Full diff: https://github.com/llvm/llvm-project/pull/115241.diff 1 Files Affected:
diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h
index 6edd3474d4edae..81e96ed65c47bf 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -462,6 +462,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
}
bool hasHIPImageSupport() const override { return HasImage; }
+
+ std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+ return std::make_pair(128, 128);
+ }
};
} // namespace targets
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arsenm
reviewed
Nov 7, 2024
Summary: The cache line size on AMDGPU varies between 64 and 128 (The lowest L2 cache also goes to 256 on some architectures.) This macro is intended to present a size that will not cause destructive interference, so we choose the larger of those values.
shiltian
approved these changes
Nov 7, 2024
arsenm
reviewed
Nov 7, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/123/builds/8923 Here is the relevant piece of the build log for the reference |
Groverkss
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to iree-org/llvm-project
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Nov 15, 2024
Summary: The cache line size on AMDGPU varies between 64 and 128 (The lowest L2 cache also goes to 256 on some architectures.) This macro is intended to present a size that will not cause destructive interference, so we choose the larger of those values.
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Summary:
The cache line size on AMDGPU varies between 64 and 128 (The lowest L2
cache also goes to 256 on some architectures.) This macro is intended to
present a size that will not cause destructive interference, so we
choose the larger of those values.