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[AMDGPU] Allow lane-op lowering for some illegal types #114887

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[AMDGPU] Allow lane-op lowering for some illegal types #114887

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9f02e25
[AMDGPU] Allow lane-op lowering for illegal types
rampitec Nov 4, 2024
6cc8a46
Added amdgcn_update_dpp
rampitec Nov 5, 2024
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12 changes: 12 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -6552,6 +6552,18 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(LoadVal);
return;
}
case Intrinsic::amdgcn_readlane:
case Intrinsic::amdgcn_readfirstlane:
case Intrinsic::amdgcn_writelane:
case Intrinsic::amdgcn_permlane16:
case Intrinsic::amdgcn_permlanex16:
case Intrinsic::amdgcn_permlane64:
case Intrinsic::amdgcn_set_inactive:
case Intrinsic::amdgcn_set_inactive_chain_arg:
case Intrinsic::amdgcn_mov_dpp8:
case Intrinsic::amdgcn_update_dpp:
Results.push_back(lowerLaneOp(*this, N, DAG));
return;
}
break;
}
Expand Down
19 changes: 19 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
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Expand Up @@ -186,6 +186,25 @@ define amdgpu_ps void @dpp8_double(double %in, ptr addrspace(1) %out) {
ret void
}

; GFX10PLUS-LABEL: {{^}}dpp8_i8:
; GFX10PLUS: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]
; GFX10PLUS: global_store_{{byte|b8}} v[1:2], v0, off
define amdgpu_ps void @dpp8_i8(i8 %in, ptr addrspace(1) %out) {
%tmp0 = call i8 @llvm.amdgcn.mov.dpp8.i8(i8 %in, i32 1)
store i8 %tmp0, ptr addrspace(1) %out
ret void
}

; GFX10PLUS-LABEL: {{^}}dpp8_i1:
; GFX10PLUS: v_mov_b32_dpp v0, v0 dpp8:[1,0,0,0,0,0,0,0]
; GFX10PLUS: v_and_b32_e32 v0, 1, v0
; GFX10PLUS: global_store_{{byte|b8}} v[1:2], v0, off
define amdgpu_ps void @dpp8_i1(i1 %in, ptr addrspace(1) %out) {
%tmp0 = call i1 @llvm.amdgcn.mov.dpp8.i1(i1 %in, i32 1)
store i1 %tmp0, ptr addrspace(1) %out
ret void
}

declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #0

attributes #0 = { nounwind readnone convergent }
162 changes: 162 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
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Expand Up @@ -8932,6 +8932,87 @@ define void @v_permlane16_v2f32(ptr addrspace(1) %out, <2 x float> %src0, i32 %s
ret void
}

define void @v_permlane16_i8(ptr addrspace(1) %out, i8 %src0, i32 %src1, i32 %src2) {
; GFX10-LABEL: v_permlane16_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_readfirstlane_b32 s5, v4
; GFX10-NEXT: v_permlane16_b32 v2, v2, s4, s5
; GFX10-NEXT: global_store_byte v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_permlane16_i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX11-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_permlane16_i8:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b8 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%v = call i8 @llvm.amdgcn.permlane16.i8(i8 %src0, i8 %src0, i32 %src1, i32 %src2, i1 false, i1 false)
store i8 %v, ptr addrspace(1) %out
ret void
}

define void @v_permlane16_i1(ptr addrspace(1) %out, i1 %src0, i32 %src1, i32 %src2) {
; GFX10-LABEL: v_permlane16_i1:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_readfirstlane_b32 s5, v4
; GFX10-NEXT: v_permlane16_b32 v2, v2, s4, s5
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
; GFX10-NEXT: global_store_byte v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_permlane16_i1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_permlane16_i1:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-NEXT: v_and_b32_e32 v2, 1, v2
; GFX12-NEXT: global_store_b8 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%v = call i1 @llvm.amdgcn.permlane16.i1(i1 %src0, i1 %src0, i32 %src1, i32 %src2, i1 false, i1 false)
store i1 %v, ptr addrspace(1) %out
ret void
}

define void @v_permlanex16_v2f32(ptr addrspace(1) %out, <2 x float> %src0, i32 %src1, i32 %src2) {
; GFX10-SDAG-LABEL: v_permlanex16_v2f32:
; GFX10-SDAG: ; %bb.0:
Expand Down Expand Up @@ -9430,3 +9511,84 @@ define void @v_permlanex16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %sr
store <8 x i16> %v, ptr addrspace(1) %out
ret void
}

define void @v_permlanex16_i8(ptr addrspace(1) %out, i8 %src0, i32 %src1, i32 %src2) {
; GFX10-LABEL: v_permlanex16_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_readfirstlane_b32 s5, v4
; GFX10-NEXT: v_permlanex16_b32 v2, v2, s4, s5
; GFX10-NEXT: global_store_byte v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_permlanex16_i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX11-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_permlanex16_i8:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b8 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%v = call i8 @llvm.amdgcn.permlanex16.i8(i8 %src0, i8 %src0, i32 %src1, i32 %src2, i1 false, i1 false)
store i8 %v, ptr addrspace(1) %out
ret void
}

define void @v_permlanex16_i1(ptr addrspace(1) %out, i1 %src0, i32 %src1, i32 %src2) {
; GFX10-LABEL: v_permlanex16_i1:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
; GFX10-NEXT: v_readfirstlane_b32 s5, v4
; GFX10-NEXT: v_permlanex16_b32 v2, v2, s4, s5
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
; GFX10-NEXT: global_store_byte v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_permlanex16_i1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_permlanex16_i1:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-NEXT: v_and_b32_e32 v2, 1, v2
; GFX12-NEXT: global_store_b8 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%v = call i1 @llvm.amdgcn.permlanex16.i1(i1 %src0, i1 %src0, i32 %src1, i32 %src2, i1 false, i1 false)
store i1 %v, ptr addrspace(1) %out
ret void
}
27 changes: 27 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
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Expand Up @@ -52,6 +52,33 @@ define amdgpu_kernel void @test_v(ptr addrspace(1) %out, i32 %src0) #1 {
store i32 %v, ptr addrspace(1) %out
ret void
}

define void @test_i8(ptr addrspace(1) %out, i8 %src0) #1 {
; GFX11-LABEL: test_i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_permlane64_b32 v2, v2
; GFX11-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
%v = call i8 @llvm.amdgcn.permlane64.i8(i8 %src0)
store i8 %v, ptr addrspace(1) %out
ret void
}

define void @test_i1(ptr addrspace(1) %out, i1 %src0) #1 {
; GFX11-LABEL: test_i1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_permlane64_b32 v2, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
%v = call i1 @llvm.amdgcn.permlane64.i1(i1 %src0)
store i1 %v, ptr addrspace(1) %out
ret void
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11-GISEL: {{.*}}
; GFX11-SDAG: {{.*}}
47 changes: 47 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
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Expand Up @@ -1729,3 +1729,50 @@ define void @test_readfirstlane_v32f16(ptr addrspace(1) %out, <32 x half> %src)
ret void
}

define void @dpp8_i8(i8 %in, ptr addrspace(1) %out) {
; CHECK-SDAG-LABEL: dpp8_i8:
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s4, v0
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s4
; CHECK-SDAG-NEXT: flat_store_byte v[1:2], v0
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0)
; CHECK-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; CHECK-GISEL-LABEL: dpp8_i8:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s4
; CHECK-GISEL-NEXT: flat_store_byte v[1:2], v0
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
; CHECK-GISEL-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call i8 @llvm.amdgcn.readfirstlane.i8(i8 %in)
store i8 %tmp0, ptr addrspace(1) %out
ret void
}

define void @dpp8_i1(i1 %in, ptr addrspace(1) %out) {
; CHECK-SDAG-LABEL: dpp8_i1:
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s4, v0
; CHECK-SDAG-NEXT: s_and_b32 s4, s4, 1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s4
; CHECK-SDAG-NEXT: flat_store_byte v[1:2], v0
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0)
; CHECK-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; CHECK-GISEL-LABEL: dpp8_i1:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; CHECK-GISEL-NEXT: s_and_b32 s4, s4, 1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s4
; CHECK-GISEL-NEXT: flat_store_byte v[1:2], v0
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
; CHECK-GISEL-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call i1 @llvm.amdgcn.readfirstlane.i1(i1 %in)
store i1 %tmp0, ptr addrspace(1) %out
ret void
}
48 changes: 48 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
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Expand Up @@ -894,6 +894,54 @@ define void @test_readlane_v8i16(ptr addrspace(1) %out, <8 x i16> %src, i32 %src
ret void
}

define void @dpp8_i8(i8 %in, ptr addrspace(1) %out) {
; CHECK-SDAG-LABEL: dpp8_i8:
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-SDAG-NEXT: v_readlane_b32 s4, v0, 1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s4
; CHECK-SDAG-NEXT: flat_store_byte v[1:2], v0
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0)
; CHECK-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; CHECK-GISEL-LABEL: dpp8_i8:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-GISEL-NEXT: v_readlane_b32 s4, v0, 1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s4
; CHECK-GISEL-NEXT: flat_store_byte v[1:2], v0
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
; CHECK-GISEL-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call i8 @llvm.amdgcn.readlane.i8(i8 %in, i32 1)
store i8 %tmp0, ptr addrspace(1) %out
ret void
}

define void @dpp8_i1(i1 %in, ptr addrspace(1) %out) {
; CHECK-SDAG-LABEL: dpp8_i1:
; CHECK-SDAG: ; %bb.0:
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-SDAG-NEXT: v_readlane_b32 s4, v0, 1
; CHECK-SDAG-NEXT: s_and_b32 s4, s4, 1
; CHECK-SDAG-NEXT: v_mov_b32_e32 v0, s4
; CHECK-SDAG-NEXT: flat_store_byte v[1:2], v0
; CHECK-SDAG-NEXT: s_waitcnt vmcnt(0)
; CHECK-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; CHECK-GISEL-LABEL: dpp8_i1:
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-GISEL-NEXT: v_readlane_b32 s4, v0, 1
; CHECK-GISEL-NEXT: s_and_b32 s4, s4, 1
; CHECK-GISEL-NEXT: v_mov_b32_e32 v0, s4
; CHECK-GISEL-NEXT: flat_store_byte v[1:2], v0
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0)
; CHECK-GISEL-NEXT: s_setpc_b64 s[30:31]
%tmp0 = call i1 @llvm.amdgcn.readlane.i1(i1 %in, i32 1)
store i1 %tmp0, ptr addrspace(1) %out
ret void
}

declare i32 @llvm.amdgcn.workitem.id.x() #2

attributes #0 = { nounwind readnone convergent }
Expand Down
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