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Merged
merged 10 commits into from
Nov 7, 2024
Merged

[Backend] Add clearSubtargetMap API for TargetMachine. #112383

merged 10 commits into from
Nov 7, 2024

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weiweichen
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@weiweichen weiweichen commented Oct 15, 2024 •
edited by wangleiat
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  • Add clearSubtargetInfo API to TargetMachine and each backend to make it possible to release memory used in each backend's SubtargetInfo map if needed. Keep this API as protected so that it will be used with precautions.

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llvmbot commented Oct 15, 2024 •
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@llvm/pr-subscribers-backend-m68k
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-backend-systemz
@llvm/pr-subscribers-backend-webassembly

@llvm/pr-subscribers-backend-x86

Author: weiwei chen (weiweichen)

Changes
  • Add clearSubtargetInfo API to TargetMachine and each backend to make it possible to release memory used in each backend's SubtargetInfo map if needed. Keep this API as protected so that it will be used with precautions.

Full diff: https://github.com/llvm/llvm-project/pull/112383.diff

33 Files Affected:

  • (modified) llvm/include/llvm/Target/TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.h (+3)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.h (+3)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.h (+3)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.h (+3)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.h (+3)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.h (+3)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.h (+3)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.h (+3)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h (+3)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.h (+3)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.h (+3)
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index c3e9d41315f617..d16fe6aa4bde55 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {
 
   void initAsmInfo();
 
+  /// clear target specific SubtargetMap.
+  virtual void clearSubtargetMap(){};
+
 public:
   /// Get a TargetTransformInfo implementation for the target.
   ///
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 7b0ae23358673e..d8c23de22386d4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -272,6 +272,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64GlobalsTaggingPass(*PR);
 }
 
+void AArch64TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 1a470ca87127ce..135a21dbde5221 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -26,6 +26,9 @@ class AArch64TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f90118f4caae38 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -938,6 +938,8 @@ bool AMDGPUTargetMachine::splitModule(
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
+void GCNTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); };
+
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index af8476bc21ec61..d2d3a64a08185f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -81,6 +81,9 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index a1a60b8bdfa9ee..e65e90c688ee05 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -50,6 +50,8 @@ static MachineSchedRegistry R600SchedRegistry("r600",
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
+void R600TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index b7f123a07a9c1d..c09d784a0a03c1 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -29,6 +29,9 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7553778c574033..fac3892d1289e9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -640,3 +640,5 @@ bool ARMBaseTargetMachine::parseMachineFunctionInfo(
   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
   return false;
 }
+
+void ARMBaseTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 69d8fa8ada6498..bf5a008e75e9ca 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -38,6 +38,9 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index a756061e307a44..45752572f0a28b 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -96,6 +96,8 @@ MachineFunctionInfo *CSKYTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void CSKYTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class CSKYPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
index e47b514ae9ddc5..872648b6d99401 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
@@ -24,6 +24,9 @@ class CSKYTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 803b9b81045c63..6cab7906b22ada 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -348,6 +348,8 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
 
 HexagonTargetMachine::~HexagonTargetMachine() = default;
 
+void HexagonTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 6e9a78b7665042..21730d88e17f4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -26,6 +26,9 @@ class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 4401aadfe78485..83e2bdf6d14f90 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -141,6 +141,8 @@ MachineFunctionInfo *LoongArchTargetMachine::createMachineFunctionInfo(
       Allocator, F, STI);
 }
 
+void LoongArchTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class LoongArchPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index fa9bc7608e7d2c..321cfdd9f84b51 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -23,6 +23,9 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index b65de5e177b53e..3353f1d34ffbd0 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -138,6 +138,8 @@ MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void M68kTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index 4ff4c4cb46b809..416fc166940672 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -34,6 +34,9 @@ class M68kTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<M68kSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 7802767e31c2f6..11c3aa12c357dc 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -215,6 +215,8 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 }
 
+void MipsTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// Mips Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 0ad239e3bed128..1efbd355a39e6e 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -36,6 +36,9 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 7d0455942923dd..08a6d4608d5e52 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -410,6 +410,8 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void PPCTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 9d0d3e727170a3..88a5d62d191b96 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -36,6 +36,9 @@ class PPCTargetMachine final : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..adfd98093df591 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -271,6 +271,8 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return true;
 }
 
+void RISCVTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index ce7b7907e1f3af..b8f7077b14a2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -25,6 +25,9 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 50a96368bbdca9..a4816fb643048b 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -158,6 +158,8 @@ MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
                                                                     F, STI);
 }
 
+void SparcTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 497d5f6623cd30..7f41d946578afc 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -25,6 +25,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 53ed46f14f14dc..a2cb9477f7c2d2 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -205,6 +205,8 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void SystemZTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 75e5d68e74eef4..db5bba172e4787 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -29,6 +29,9 @@ class SystemZTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 73765f8fa0092c..c499a4a95bf2f5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -185,6 +185,8 @@ WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
   return getSubtargetImpl(CPU, FS);
 }
 
+void WebAssemblyTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index 1ff2e175978c31..e532a6237aa578 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -26,6 +26,9 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
   bool UsesMultivalueABI = false;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index fc2a1e34b711ef..187c856740376d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -373,6 +373,8 @@ bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return SrcAS < 256 && DestAS < 256;
 }
 
+void X86TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index ec4a93e9c9d4b0..93fa5a562ecc1d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -31,6 +31,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
   // True if this is used in JIT.
   bool IsJIT;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 49c7faf84df1d3..4279e4edacce40 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -83,6 +83,8 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void XtensaTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Xtensa Code Generator Pass Configuration Options.
 class XtensaPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index f371f22ed3d0e7..041b01f6c87f91 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -47,6 +47,9 @@ class XtensaTargetMachine : public LLVMTargetMachine {
 
 protected:
   mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
+
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
 };
 } // end namespace llvm

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llvmbot commented Oct 15, 2024

@llvm/pr-subscribers-backend-risc-v

Author: weiwei chen (weiweichen)

Changes
  • Add clearSubtargetInfo API to TargetMachine and each backend to make it possible to release memory used in each backend's SubtargetInfo map if needed. Keep this API as protected so that it will be used with precautions.

Full diff: https://github.com/llvm/llvm-project/pull/112383.diff

33 Files Affected:

  • (modified) llvm/include/llvm/Target/TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.h (+3)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.h (+3)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.h (+3)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.h (+3)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.h (+3)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.h (+3)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.h (+3)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.h (+3)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h (+3)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.h (+3)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.h (+3)
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index c3e9d41315f617..d16fe6aa4bde55 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {
 
   void initAsmInfo();
 
+  /// clear target specific SubtargetMap.
+  virtual void clearSubtargetMap(){};
+
 public:
   /// Get a TargetTransformInfo implementation for the target.
   ///
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 7b0ae23358673e..d8c23de22386d4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -272,6 +272,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64GlobalsTaggingPass(*PR);
 }
 
+void AArch64TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 1a470ca87127ce..135a21dbde5221 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -26,6 +26,9 @@ class AArch64TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f90118f4caae38 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -938,6 +938,8 @@ bool AMDGPUTargetMachine::splitModule(
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
+void GCNTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); };
+
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index af8476bc21ec61..d2d3a64a08185f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -81,6 +81,9 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index a1a60b8bdfa9ee..e65e90c688ee05 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -50,6 +50,8 @@ static MachineSchedRegistry R600SchedRegistry("r600",
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
+void R600TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index b7f123a07a9c1d..c09d784a0a03c1 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -29,6 +29,9 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7553778c574033..fac3892d1289e9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -640,3 +640,5 @@ bool ARMBaseTargetMachine::parseMachineFunctionInfo(
   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
   return false;
 }
+
+void ARMBaseTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 69d8fa8ada6498..bf5a008e75e9ca 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -38,6 +38,9 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index a756061e307a44..45752572f0a28b 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -96,6 +96,8 @@ MachineFunctionInfo *CSKYTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void CSKYTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class CSKYPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
index e47b514ae9ddc5..872648b6d99401 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
@@ -24,6 +24,9 @@ class CSKYTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 803b9b81045c63..6cab7906b22ada 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -348,6 +348,8 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
 
 HexagonTargetMachine::~HexagonTargetMachine() = default;
 
+void HexagonTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 6e9a78b7665042..21730d88e17f4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -26,6 +26,9 @@ class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 4401aadfe78485..83e2bdf6d14f90 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -141,6 +141,8 @@ MachineFunctionInfo *LoongArchTargetMachine::createMachineFunctionInfo(
       Allocator, F, STI);
 }
 
+void LoongArchTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class LoongArchPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index fa9bc7608e7d2c..321cfdd9f84b51 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -23,6 +23,9 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index b65de5e177b53e..3353f1d34ffbd0 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -138,6 +138,8 @@ MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void M68kTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index 4ff4c4cb46b809..416fc166940672 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -34,6 +34,9 @@ class M68kTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<M68kSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 7802767e31c2f6..11c3aa12c357dc 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -215,6 +215,8 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 }
 
+void MipsTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// Mips Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 0ad239e3bed128..1efbd355a39e6e 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -36,6 +36,9 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 7d0455942923dd..08a6d4608d5e52 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -410,6 +410,8 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void PPCTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 9d0d3e727170a3..88a5d62d191b96 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -36,6 +36,9 @@ class PPCTargetMachine final : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..adfd98093df591 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -271,6 +271,8 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return true;
 }
 
+void RISCVTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index ce7b7907e1f3af..b8f7077b14a2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -25,6 +25,9 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 50a96368bbdca9..a4816fb643048b 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -158,6 +158,8 @@ MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
                                                                     F, STI);
 }
 
+void SparcTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 497d5f6623cd30..7f41d946578afc 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -25,6 +25,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 53ed46f14f14dc..a2cb9477f7c2d2 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -205,6 +205,8 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void SystemZTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 75e5d68e74eef4..db5bba172e4787 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -29,6 +29,9 @@ class SystemZTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 73765f8fa0092c..c499a4a95bf2f5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -185,6 +185,8 @@ WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
   return getSubtargetImpl(CPU, FS);
 }
 
+void WebAssemblyTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index 1ff2e175978c31..e532a6237aa578 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -26,6 +26,9 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
   bool UsesMultivalueABI = false;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index fc2a1e34b711ef..187c856740376d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -373,6 +373,8 @@ bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return SrcAS < 256 && DestAS < 256;
 }
 
+void X86TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index ec4a93e9c9d4b0..93fa5a562ecc1d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -31,6 +31,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
   // True if this is used in JIT.
   bool IsJIT;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 49c7faf84df1d3..4279e4edacce40 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -83,6 +83,8 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void XtensaTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Xtensa Code Generator Pass Configuration Options.
 class XtensaPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index f371f22ed3d0e7..041b01f6c87f91 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -47,6 +47,9 @@ class XtensaTargetMachine : public LLVMTargetMachine {
 
 protected:
   mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
+
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
 };
 } // end namespace llvm

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llvmbot commented Oct 15, 2024

@llvm/pr-subscribers-backend-sparc

Author: weiwei chen (weiweichen)

Changes
  • Add clearSubtargetInfo API to TargetMachine and each backend to make it possible to release memory used in each backend's SubtargetInfo map if needed. Keep this API as protected so that it will be used with precautions.

Full diff: https://github.com/llvm/llvm-project/pull/112383.diff

33 Files Affected:

  • (modified) llvm/include/llvm/Target/TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.h (+3)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.h (+3)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.h (+3)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.h (+3)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.h (+3)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.h (+3)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.h (+3)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.h (+3)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h (+3)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.h (+3)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.h (+3)
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index c3e9d41315f617..d16fe6aa4bde55 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {
 
   void initAsmInfo();
 
+  /// clear target specific SubtargetMap.
+  virtual void clearSubtargetMap(){};
+
 public:
   /// Get a TargetTransformInfo implementation for the target.
   ///
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 7b0ae23358673e..d8c23de22386d4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -272,6 +272,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64GlobalsTaggingPass(*PR);
 }
 
+void AArch64TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 1a470ca87127ce..135a21dbde5221 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -26,6 +26,9 @@ class AArch64TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f90118f4caae38 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -938,6 +938,8 @@ bool AMDGPUTargetMachine::splitModule(
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
+void GCNTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); };
+
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index af8476bc21ec61..d2d3a64a08185f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -81,6 +81,9 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index a1a60b8bdfa9ee..e65e90c688ee05 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -50,6 +50,8 @@ static MachineSchedRegistry R600SchedRegistry("r600",
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
+void R600TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index b7f123a07a9c1d..c09d784a0a03c1 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -29,6 +29,9 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7553778c574033..fac3892d1289e9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -640,3 +640,5 @@ bool ARMBaseTargetMachine::parseMachineFunctionInfo(
   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
   return false;
 }
+
+void ARMBaseTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 69d8fa8ada6498..bf5a008e75e9ca 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -38,6 +38,9 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index a756061e307a44..45752572f0a28b 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -96,6 +96,8 @@ MachineFunctionInfo *CSKYTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void CSKYTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class CSKYPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
index e47b514ae9ddc5..872648b6d99401 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
@@ -24,6 +24,9 @@ class CSKYTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 803b9b81045c63..6cab7906b22ada 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -348,6 +348,8 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
 
 HexagonTargetMachine::~HexagonTargetMachine() = default;
 
+void HexagonTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 6e9a78b7665042..21730d88e17f4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -26,6 +26,9 @@ class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 4401aadfe78485..83e2bdf6d14f90 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -141,6 +141,8 @@ MachineFunctionInfo *LoongArchTargetMachine::createMachineFunctionInfo(
       Allocator, F, STI);
 }
 
+void LoongArchTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class LoongArchPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index fa9bc7608e7d2c..321cfdd9f84b51 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -23,6 +23,9 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index b65de5e177b53e..3353f1d34ffbd0 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -138,6 +138,8 @@ MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void M68kTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index 4ff4c4cb46b809..416fc166940672 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -34,6 +34,9 @@ class M68kTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<M68kSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 7802767e31c2f6..11c3aa12c357dc 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -215,6 +215,8 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 }
 
+void MipsTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// Mips Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 0ad239e3bed128..1efbd355a39e6e 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -36,6 +36,9 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 7d0455942923dd..08a6d4608d5e52 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -410,6 +410,8 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void PPCTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 9d0d3e727170a3..88a5d62d191b96 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -36,6 +36,9 @@ class PPCTargetMachine final : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..adfd98093df591 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -271,6 +271,8 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return true;
 }
 
+void RISCVTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index ce7b7907e1f3af..b8f7077b14a2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -25,6 +25,9 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 50a96368bbdca9..a4816fb643048b 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -158,6 +158,8 @@ MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
                                                                     F, STI);
 }
 
+void SparcTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 497d5f6623cd30..7f41d946578afc 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -25,6 +25,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 53ed46f14f14dc..a2cb9477f7c2d2 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -205,6 +205,8 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void SystemZTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 75e5d68e74eef4..db5bba172e4787 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -29,6 +29,9 @@ class SystemZTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 73765f8fa0092c..c499a4a95bf2f5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -185,6 +185,8 @@ WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
   return getSubtargetImpl(CPU, FS);
 }
 
+void WebAssemblyTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index 1ff2e175978c31..e532a6237aa578 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -26,6 +26,9 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
   bool UsesMultivalueABI = false;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index fc2a1e34b711ef..187c856740376d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -373,6 +373,8 @@ bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return SrcAS < 256 && DestAS < 256;
 }
 
+void X86TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index ec4a93e9c9d4b0..93fa5a562ecc1d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -31,6 +31,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
   // True if this is used in JIT.
   bool IsJIT;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 49c7faf84df1d3..4279e4edacce40 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -83,6 +83,8 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void XtensaTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Xtensa Code Generator Pass Configuration Options.
 class XtensaPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index f371f22ed3d0e7..041b01f6c87f91 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -47,6 +47,9 @@ class XtensaTargetMachine : public LLVMTargetMachine {
 
 protected:
   mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
+
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
 };
 } // end namespace llvm

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llvmbot commented Oct 15, 2024

@llvm/pr-subscribers-backend-hexagon

Author: weiwei chen (weiweichen)

Changes
  • Add clearSubtargetInfo API to TargetMachine and each backend to make it possible to release memory used in each backend's SubtargetInfo map if needed. Keep this API as protected so that it will be used with precautions.

Full diff: https://github.com/llvm/llvm-project/pull/112383.diff

33 Files Affected:

  • (modified) llvm/include/llvm/Target/TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.h (+3)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.h (+3)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.h (+3)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.h (+3)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.h (+3)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.h (+3)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.h (+3)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.h (+3)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h (+3)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.h (+3)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.h (+3)
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index c3e9d41315f617..d16fe6aa4bde55 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {
 
   void initAsmInfo();
 
+  /// clear target specific SubtargetMap.
+  virtual void clearSubtargetMap(){};
+
 public:
   /// Get a TargetTransformInfo implementation for the target.
   ///
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 7b0ae23358673e..d8c23de22386d4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -272,6 +272,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64GlobalsTaggingPass(*PR);
 }
 
+void AArch64TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 1a470ca87127ce..135a21dbde5221 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -26,6 +26,9 @@ class AArch64TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f90118f4caae38 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -938,6 +938,8 @@ bool AMDGPUTargetMachine::splitModule(
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
+void GCNTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); };
+
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index af8476bc21ec61..d2d3a64a08185f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -81,6 +81,9 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index a1a60b8bdfa9ee..e65e90c688ee05 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -50,6 +50,8 @@ static MachineSchedRegistry R600SchedRegistry("r600",
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
+void R600TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index b7f123a07a9c1d..c09d784a0a03c1 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -29,6 +29,9 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7553778c574033..fac3892d1289e9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -640,3 +640,5 @@ bool ARMBaseTargetMachine::parseMachineFunctionInfo(
   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
   return false;
 }
+
+void ARMBaseTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 69d8fa8ada6498..bf5a008e75e9ca 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -38,6 +38,9 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index a756061e307a44..45752572f0a28b 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -96,6 +96,8 @@ MachineFunctionInfo *CSKYTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void CSKYTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class CSKYPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
index e47b514ae9ddc5..872648b6d99401 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
@@ -24,6 +24,9 @@ class CSKYTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 803b9b81045c63..6cab7906b22ada 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -348,6 +348,8 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
 
 HexagonTargetMachine::~HexagonTargetMachine() = default;
 
+void HexagonTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 6e9a78b7665042..21730d88e17f4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -26,6 +26,9 @@ class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 4401aadfe78485..83e2bdf6d14f90 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -141,6 +141,8 @@ MachineFunctionInfo *LoongArchTargetMachine::createMachineFunctionInfo(
       Allocator, F, STI);
 }
 
+void LoongArchTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class LoongArchPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index fa9bc7608e7d2c..321cfdd9f84b51 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -23,6 +23,9 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index b65de5e177b53e..3353f1d34ffbd0 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -138,6 +138,8 @@ MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void M68kTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index 4ff4c4cb46b809..416fc166940672 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -34,6 +34,9 @@ class M68kTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<M68kSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 7802767e31c2f6..11c3aa12c357dc 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -215,6 +215,8 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 }
 
+void MipsTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// Mips Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 0ad239e3bed128..1efbd355a39e6e 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -36,6 +36,9 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 7d0455942923dd..08a6d4608d5e52 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -410,6 +410,8 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void PPCTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 9d0d3e727170a3..88a5d62d191b96 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -36,6 +36,9 @@ class PPCTargetMachine final : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..adfd98093df591 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -271,6 +271,8 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return true;
 }
 
+void RISCVTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index ce7b7907e1f3af..b8f7077b14a2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -25,6 +25,9 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 50a96368bbdca9..a4816fb643048b 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -158,6 +158,8 @@ MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
                                                                     F, STI);
 }
 
+void SparcTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 497d5f6623cd30..7f41d946578afc 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -25,6 +25,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 53ed46f14f14dc..a2cb9477f7c2d2 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -205,6 +205,8 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void SystemZTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 75e5d68e74eef4..db5bba172e4787 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -29,6 +29,9 @@ class SystemZTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 73765f8fa0092c..c499a4a95bf2f5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -185,6 +185,8 @@ WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
   return getSubtargetImpl(CPU, FS);
 }
 
+void WebAssemblyTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index 1ff2e175978c31..e532a6237aa578 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -26,6 +26,9 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
   bool UsesMultivalueABI = false;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index fc2a1e34b711ef..187c856740376d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -373,6 +373,8 @@ bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return SrcAS < 256 && DestAS < 256;
 }
 
+void X86TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index ec4a93e9c9d4b0..93fa5a562ecc1d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -31,6 +31,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
   // True if this is used in JIT.
   bool IsJIT;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 49c7faf84df1d3..4279e4edacce40 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -83,6 +83,8 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void XtensaTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Xtensa Code Generator Pass Configuration Options.
 class XtensaPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index f371f22ed3d0e7..041b01f6c87f91 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -47,6 +47,9 @@ class XtensaTargetMachine : public LLVMTargetMachine {
 
 protected:
   mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
+
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
 };
 } // end namespace llvm

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llvmbot commented Oct 15, 2024

@llvm/pr-subscribers-backend-powerpc

Author: weiwei chen (weiweichen)

Changes
  • Add clearSubtargetInfo API to TargetMachine and each backend to make it possible to release memory used in each backend's SubtargetInfo map if needed. Keep this API as protected so that it will be used with precautions.

Full diff: https://github.com/llvm/llvm-project/pull/112383.diff

33 Files Affected:

  • (modified) llvm/include/llvm/Target/TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h (+3)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.h (+3)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/ARM/ARMTargetMachine.h (+3)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/CSKY/CSKYTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Hexagon/HexagonTargetMachine.h (+3)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/LoongArch/LoongArchTargetMachine.h (+3)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/M68k/M68kTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Mips/MipsTargetMachine.h (+3)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.h (+3)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (+3)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Sparc/SparcTargetMachine.h (+3)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/SystemZ/SystemZTargetMachine.h (+3)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h (+3)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/X86/X86TargetMachine.h (+3)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp (+2)
  • (modified) llvm/lib/Target/Xtensa/XtensaTargetMachine.h (+3)
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index c3e9d41315f617..d16fe6aa4bde55 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {
 
   void initAsmInfo();
 
+  /// clear target specific SubtargetMap.
+  virtual void clearSubtargetMap(){};
+
 public:
   /// Get a TargetTransformInfo implementation for the target.
   ///
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 7b0ae23358673e..d8c23de22386d4 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -272,6 +272,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64GlobalsTaggingPass(*PR);
 }
 
+void AArch64TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 1a470ca87127ce..135a21dbde5221 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -26,6 +26,9 @@ class AArch64TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 23ee0c3e896eb3..f90118f4caae38 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -938,6 +938,8 @@ bool AMDGPUTargetMachine::splitModule(
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
+void GCNTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); };
+
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index af8476bc21ec61..d2d3a64a08185f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -81,6 +81,9 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index a1a60b8bdfa9ee..e65e90c688ee05 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -50,6 +50,8 @@ static MachineSchedRegistry R600SchedRegistry("r600",
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
+void R600TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index b7f123a07a9c1d..c09d784a0a03c1 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -29,6 +29,9 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7553778c574033..fac3892d1289e9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -640,3 +640,5 @@ bool ARMBaseTargetMachine::parseMachineFunctionInfo(
   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
   return false;
 }
+
+void ARMBaseTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 69d8fa8ada6498..bf5a008e75e9ca 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -38,6 +38,9 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index a756061e307a44..45752572f0a28b 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -96,6 +96,8 @@ MachineFunctionInfo *CSKYTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void CSKYTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class CSKYPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
index e47b514ae9ddc5..872648b6d99401 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
@@ -24,6 +24,9 @@ class CSKYTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 803b9b81045c63..6cab7906b22ada 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -348,6 +348,8 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
 
 HexagonTargetMachine::~HexagonTargetMachine() = default;
 
+void HexagonTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 6e9a78b7665042..21730d88e17f4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -26,6 +26,9 @@ class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 4401aadfe78485..83e2bdf6d14f90 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -141,6 +141,8 @@ MachineFunctionInfo *LoongArchTargetMachine::createMachineFunctionInfo(
       Allocator, F, STI);
 }
 
+void LoongArchTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class LoongArchPassConfig : public TargetPassConfig {
 public:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index fa9bc7608e7d2c..321cfdd9f84b51 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -23,6 +23,9 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index b65de5e177b53e..3353f1d34ffbd0 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -138,6 +138,8 @@ MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void M68kTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index 4ff4c4cb46b809..416fc166940672 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -34,6 +34,9 @@ class M68kTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<M68kSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 7802767e31c2f6..11c3aa12c357dc 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -215,6 +215,8 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 }
 
+void MipsTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// Mips Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 0ad239e3bed128..1efbd355a39e6e 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -36,6 +36,9 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 7d0455942923dd..08a6d4608d5e52 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -410,6 +410,8 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void PPCTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 9d0d3e727170a3..88a5d62d191b96 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -36,6 +36,9 @@ class PPCTargetMachine final : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..adfd98093df591 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -271,6 +271,8 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return true;
 }
 
+void RISCVTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index ce7b7907e1f3af..b8f7077b14a2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -25,6 +25,9 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 50a96368bbdca9..a4816fb643048b 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -158,6 +158,8 @@ MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
                                                                     F, STI);
 }
 
+void SparcTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 497d5f6623cd30..7f41d946578afc 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -25,6 +25,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 53ed46f14f14dc..a2cb9477f7c2d2 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -205,6 +205,8 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void SystemZTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 75e5d68e74eef4..db5bba172e4787 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -29,6 +29,9 @@ class SystemZTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 73765f8fa0092c..c499a4a95bf2f5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -185,6 +185,8 @@ WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
   return getSubtargetImpl(CPU, FS);
 }
 
+void WebAssemblyTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index 1ff2e175978c31..e532a6237aa578 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -26,6 +26,9 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
   bool UsesMultivalueABI = false;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index fc2a1e34b711ef..187c856740376d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -373,6 +373,8 @@ bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return SrcAS < 256 && DestAS < 256;
 }
 
+void X86TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index ec4a93e9c9d4b0..93fa5a562ecc1d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -31,6 +31,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
   // True if this is used in JIT.
   bool IsJIT;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 49c7faf84df1d3..4279e4edacce40 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -83,6 +83,8 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void XtensaTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Xtensa Code Generator Pass Configuration Options.
 class XtensaPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index f371f22ed3d0e7..041b01f6c87f91 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -47,6 +47,9 @@ class XtensaTargetMachine : public LLVMTargetMachine {
 
 protected:
   mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
+
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
 };
 } // end namespace llvm

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✅ With the latest revision this PR passed the C/C++ code formatter.

arsenm
arsenm reviewed Oct 15, 2024
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I think this is too specific. What is the use case for this? If you're tearing down the TargetMachine, I would expect to release everything. If you're reusing the TargetMachine, I would also expect to just leave everything as it is

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weiweichen commented Oct 15, 2024 •
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I think this is too specific. What is the use case for this? If you're tearing down the TargetMachine, I would expect to release everything. If you're reusing the TargetMachine, I would also expect to just leave everything as it is

I don't want to tear down the whole TargetMachine, I just want to release the memory in this map specifically and dedup them into a centralized place to reduce memory footprint when I have multiple TargetMachines running in parallel in the system.

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arsenm commented Oct 15, 2024

I don't want to tear down the whole TargetMachine, I just want to release the memory in this map specifically and dedup them into a centralized place to reduce memory footprint when I have multiple TargetMachines running in parallel in the system.

Why do you need multiple TargetMachines from the same target to compile in parallel?

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I don't want to tear down the whole TargetMachine, I just want to release the memory in this map specifically and dedup them into a centralized place to reduce memory footprint when I have multiple TargetMachines running in parallel in the system.

Why do you need multiple TargetMachines from the same target to compile in parallel?

To parallelize llvm compilation for more efficient compilation time.

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arsenm commented Oct 15, 2024

To parallelize llvm compilation for more efficient compilation time.

But I would expect you can use one machine for different compilations. Is the issue TargetOptions?

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To parallelize llvm compilation for more efficient compilation time.

But I would expect you can use one machine for different compilations. Is the issue TargetOptions?

Not exactly. It's the that TargetMachine (like LLVMContext and MCContext) cannot be shared among parallel llc pipelines because it's not read-only and not thread-safe. SubtargetInfo is part of TargetMachine (or rather LLVMTargetMachine), it is a StringMap to dedup those can be shared among MachineFunctions that uses the same TargetMachine, but not when there are multiple TargetMachines. This is not mainly a functionality issue but memory footprint during compilation time and can potentially reduced where there are many parallel pipelines running.

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arsenm commented Oct 15, 2024

If we had an explicit initialization of all subtargets / TargetOptions needed by a module, and made the contexts external (i.e. #111234), can you just use the one TargetMachine? Other than those, the TargetMachine should be stateless

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If we had an explicit initialization of all subtargets / TargetOptions needed by a module, and made the contexts external (i.e. #111234), can you just use the one TargetMachine? Other than those, the TargetMachine should be stateless

Yes, it would solve the problem if the initialization can be don explicitly once and the TargetMachine is stateless. Thank for pointing me to the PR! I'll take a detailed look at the it. Though one thing I notice that the PR is not changing the mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap; private/protected member in concrete TargetMachines for different backends. They are mutable and being modified mostly in the same pattern here. Is there a plan to change that to make TargetMachine fully stateless as well?

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arsenm commented Oct 15, 2024

They are mutable and being modified mostly in the same pattern here. Is there a plan to change that to make TargetMachine fully stateless as well?

No, I'm not aware of one. The other problematic piece is TargetOptions

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They are mutable and being modified mostly in the same pattern here. Is there a plan to change that to make TargetMachine fully stateless as well?

No, I'm not aware of one. The other problematic piece is TargetOptions

Oof, the change in the mentioned PR won't solve the parallel compilation memory issue then 😭

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If we had an explicit initialization of all subtargets / TargetOptions needed by a module, and made the contexts external (i.e. #111234),

If by "explicit initialization" you refer to calling getSubtargetImpl, this won't be sufficient, unfortunately. Having something like TargetMachine::setSubtarget(shared_ptr<TargetSubtargetInfo>) might help.

can you just use the one TargetMachine? Other than those, the TargetMachine should be stateless

To describe the problem a bit more: there's parallel compilation that use identical TargetMachines, but different instances. it's known that at some point TargetSubtargetInfo can be released to reduce memory footprint. Ideally, if TargetMachine is stateless, there will be no need to have different instances.

if you or @topperc can recommend what can be done in a short term, that will be great.

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arsenm commented Oct 20, 2024

If by "explicit initialization" you refer to calling getSubtargetImpl, this won't be sufficient, unfortunately. Having something like TargetMachine::setSubtarget(shared_ptr<TargetSubtargetInfo>) might help.

I mean the lazy construction of subtargets is an issue. You would have to pre-populate the map with any subtargets that are needed in the module (i.e. loop through every function and query the subtarget for each)

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I mean the lazy construction of subtargets is an issue.

I don't think lazy construction itself is an issue here: regardless if it's lazy or not, multiple instance of a target machine is going to keep subtargets alive, thus memory footprint is going to stay high for longer than needed.

You would have to pre-populate the map with any subtargets that are needed in the module (i.e. loop through every function and query the subtarget for each)

That's absolutely fine with a suggestion I made. However, I don't want to derail conversation about that patch. Does it look fine approach to be taken ?

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arsenm commented Oct 21, 2024 •
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I mean the lazy construction of subtargets is an issue.

I don't think lazy construction itself is an issue here: regardless if it's lazy or not, multiple instance of a target machine is going to keep subtargets alive, thus memory footprint is going to stay high for longer than needed.

It would be for parallelization. What I am advocating for is making it so you can do parallel compilations with a single TargetMachine instance, not one per thread.

Is the memory footprint of subtargets really so large? I thought they were pretty tiny

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I mean the lazy construction of subtargets is an issue.

I don't think lazy construction itself is an issue here: regardless if it's lazy or not, multiple instance of a target machine is going to keep subtargets alive, thus memory footprint is going to stay high for longer than needed.

It would be for parallelization. What I am advocating for is making it so you can do parallel compilations with a single TargetMachine instance, not one per thread.

Is the memory footprint of subtargets really so large? I thought they were pretty tiny

They were pretty tiny by themselves (~4M for example), but they accumulate/multiply when there are many parallel tasks (for higher-level of parallelization) and we need a barrier to collect the codegen result together before doing the final AsmPrint. We see about 60% peak memory reduce if we can release these SubtargetInfos earlier and replace them with a shared copy.

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Making the API name more general.

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Could someone take look at this PR when you have sometime? If there is no more objections in a few days, I'll merge the PR and will definitely make followups or revert if needed. Thank you!

topperc
topperc reviewed Nov 5, 2024
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llvm/include/llvm/Target/TargetMachine.h
@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {

void initAsmInfo();

/// Reset internal state.
virtual void reset() {};
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Should this be pure virtual since every target needs to implement this?

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This is a good point! Trying to balance all the review comments I got and I think I'll remove the implementation from the backend that I don't particularly care about and leave them with the default implementation here as a no-op and can always overload with specific implementations should the need arises in the future.

tjk213
tjk213 reviewed Nov 5, 2024
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I like the name-change to a general API rather than exposing the internal detail of SubtargetMap. However, with a general name like reset() I would expect the function to reset all internal state, but I'm not sure that this PR accomplishes that for all targets. We could consider raising an unimplemented error in the base class and only adding reset() to the targets that you need to be a little more defensive about it.

Other than that, this looks good to me.

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I like the name-change to a general API rather than exposing the internal detail of SubtargetMap. However, with a general name like reset() I would expect the function to reset all internal state, but I'm not sure that this PR accomplishes that for all targets. We could consider raising an unimplemented error in the base class and only adding reset() to the targets that you need to be a little more defensive about it.

Other than that, this looks good to me.

I got other reviewer's request to make the name of the function more general although the intent is to just clear the one data structure. I'm not sure how to balance that comment with yours though I agree it makes more sense to me that reset() resets all internal state.

I'll keep the general name of the API and remove the implementation for the targets I don't need for now to keep it as a no-op.

@weiweichen weiweichen merged commit c8a7f14 into llvm:main Nov 7, 2024
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Groverkss pushed a commit to iree-org/llvm-project that referenced this pull request Nov 15, 2024
@weiweichen @Groverkss
[Backend] Add clearSubtargetMap API for TargetMachine. (llvm#112383)
11e80a9 
- [x] Add `clearSubtargetInfo` API to TargetMachine and each backend to
make it possible to release memory used in each backend's
`SubtargetInfo` map if needed. Keep this API as `protected` so that it
will be used with precautions.
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