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Merged
merged 2 commits into from
Oct 14, 2024
Merged

ValueTracking: handle more ops in isNotCrossLaneOperation #112183

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ff59ad3
ValueTracking: handle more ops in isNotCrossLaneOperation
artagnon Oct 14, 2024
5275275
select-abs: drop TODO
artagnon Oct 14, 2024
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21 changes: 2 additions & 19 deletions llvm/lib/Analysis/ValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6948,25 +6948,8 @@ bool llvm::onlyUsedByLifetimeMarkersOrDroppableInsts(const Value *V) {
}

bool llvm::isNotCrossLaneOperation(const Instruction *I) {
if (auto *II = dyn_cast<IntrinsicInst>(I)) {
switch (II->getIntrinsicID()) {
// TODO: expand this list.
case Intrinsic::ctlz:
case Intrinsic::cttz:
case Intrinsic::ctpop:
case Intrinsic::umin:
case Intrinsic::umax:
case Intrinsic::smin:
case Intrinsic::smax:
case Intrinsic::usub_sat:
case Intrinsic::uadd_sat:
case Intrinsic::ssub_sat:
case Intrinsic::sadd_sat:
return true;
default:
return false;
}
}
if (auto *II = dyn_cast<IntrinsicInst>(I))
return isTriviallyVectorizable(II->getIntrinsicID());
return !isa<CallBase, BitCastInst, ShuffleVectorInst, ExtractElementInst>(I);
}

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4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
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Expand Up @@ -998,8 +998,8 @@ define nofpclass(nan inf) float @pow_f32(float nofpclass(nan inf) %arg, float no
; CHECK-NEXT: [[I12:%.*]] = select i1 [[I11]], float [[ARG]], float 1.000000e+00
; CHECK-NEXT: [[I13:%.*]] = tail call noundef float @llvm.copysign.f32(float noundef [[I4]], float noundef [[I12]])
; CHECK-NEXT: [[I17:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00
; CHECK-NEXT: [[I21:%.*]] = select i1 [[I11]], float [[ARG]], float 0.000000e+00
; CHECK-NEXT: [[I22:%.*]] = tail call noundef nofpclass(nan sub norm) float @llvm.copysign.f32(float noundef 0.000000e+00, float noundef [[I21]])
; CHECK-NEXT: [[TMP0:%.*]] = tail call nofpclass(nan sub norm) float @llvm.copysign.f32(float 0.000000e+00, float [[ARG]])
; CHECK-NEXT: [[I22:%.*]] = select i1 [[I11]], float [[TMP0]], float 0.000000e+00
; CHECK-NEXT: [[I23:%.*]] = select i1 [[I17]], float [[I22]], float [[I13]]
; CHECK-NEXT: [[I24:%.*]] = fcmp oeq float [[ARG]], 1.000000e+00
; CHECK-NEXT: [[I25:%.*]] = fcmp oeq float [[ARG1]], 0.000000e+00
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19 changes: 6 additions & 13 deletions llvm/test/Transforms/InstSimplify/select-abs.ll
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Expand Up @@ -232,14 +232,11 @@ entry:
ret i64 %res
}

; TODO: Handle vector cases?
define <4 x i16> @select_v4i16_eq0_abs_t(<4 x i16> %a) {
; CHECK-LABEL: @select_v4i16_eq0_abs_t(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND:%.*]] = icmp eq <4 x i16> [[A:%.*]], zeroinitializer
; CHECK-NEXT: [[ABS:%.*]] = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[A]], i1 true)
; CHECK-NEXT: [[RES:%.*]] = select <4 x i1> [[COND]], <4 x i16> zeroinitializer, <4 x i16> [[ABS]]
; CHECK-NEXT: ret <4 x i16> [[RES]]
; CHECK-NEXT: [[ABS:%.*]] = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[A:%.*]], i1 true)
; CHECK-NEXT: ret <4 x i16> [[ABS]]
;
entry:
%cond = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
Expand All @@ -251,10 +248,8 @@ entry:
define <4 x i16> @select_v4i16_ne0_abs_t(<4 x i16> %a) {
; CHECK-LABEL: @select_v4i16_ne0_abs_t(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND:%.*]] = icmp ne <4 x i16> [[A:%.*]], zeroinitializer
; CHECK-NEXT: [[ABS:%.*]] = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[A]], i1 true)
; CHECK-NEXT: [[RES:%.*]] = select <4 x i1> [[COND]], <4 x i16> [[ABS]], <4 x i16> zeroinitializer
; CHECK-NEXT: ret <4 x i16> [[RES]]
; CHECK-NEXT: [[ABS:%.*]] = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[A:%.*]], i1 true)
; CHECK-NEXT: ret <4 x i16> [[ABS]]
;
entry:
%cond = icmp ne <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
Expand Down Expand Up @@ -305,10 +300,8 @@ entry:
define <4 x i16> @badsplat1_select_v4i16_ne0_abs(<4 x i16> %a) {
; CHECK-LABEL: @badsplat1_select_v4i16_ne0_abs(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[COND:%.*]] = icmp ne <4 x i16> [[A:%.*]], <i16 0, i16 1, i16 0, i16 0>
; CHECK-NEXT: [[ABS:%.*]] = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[A]], i1 true)
; CHECK-NEXT: [[RES:%.*]] = select <4 x i1> [[COND]], <4 x i16> [[ABS]], <4 x i16> <i16 0, i16 1, i16 0, i16 0>
; CHECK-NEXT: ret <4 x i16> [[RES]]
; CHECK-NEXT: [[ABS:%.*]] = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[A:%.*]], i1 true)
; CHECK-NEXT: ret <4 x i16> [[ABS]]
;
entry:
%cond = icmp ne <4 x i16> %a, <i16 0, i16 1, i16 0, i16 0>
Expand Down
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