[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC #111279
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…lar to ALU(W)_r(r/i). NFC Create Unary_r and UnaryW_r that use OP_IMM and OP_IMM_32.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesCreate Unary_r and UnaryW_r that use OP_IMM and OP_IMM_32. Full diff: https://github.com/llvm/llvm-project/pull/111279.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 01ecd06e288bca..0f16b2a9739dd3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -606,6 +606,16 @@ class Priv_rr<string opcodestr, bits<7> funct7>
let rd = 0;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Unary_r<bits<12> imm12, bits<3> funct3, string opcodestr>
+ : RVInstIUnary<imm12, funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class UnaryW_r<bits<12> imm12, bits<3> funct3, string opcodestr>
+ : RVInstIUnary<imm12, funct3, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1">;
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 3dcab2def0c0ef..39eff7dcead6e3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -232,12 +232,6 @@ class RVBUnaryR<bits<7> funct7, bits<3> funct3,
let rs2 = 0;
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBUnary<bits<12> imm12, bits<3> funct3,
- RISCVOpcode opcode, string opcodestr>
- : RVInstIUnary<imm12, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
- opcodestr, "$rd, $rs1">;
-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBShift_ri<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
string opcodestr>
@@ -333,27 +327,27 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">,
} // Predicates = [HasStdExtZbkx]
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
-def CLZ : RVBUnary<0b011000000000, 0b001, OPC_OP_IMM, "clz">,
+def CLZ : Unary_r<0b011000000000, 0b001, "clz">,
Sched<[WriteCLZ, ReadCLZ]>;
-def CTZ : RVBUnary<0b011000000001, 0b001, OPC_OP_IMM, "ctz">,
+def CTZ : Unary_r<0b011000000001, 0b001, "ctz">,
Sched<[WriteCTZ, ReadCTZ]>;
-def CPOP : RVBUnary<0b011000000010, 0b001, OPC_OP_IMM, "cpop">,
+def CPOP : Unary_r<0b011000000010, 0b001, "cpop">,
Sched<[WriteCPOP, ReadCPOP]>;
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
-def CLZW : RVBUnary<0b011000000000, 0b001, OPC_OP_IMM_32, "clzw">,
- Sched<[WriteCLZ32, ReadCLZ32]>;
-def CTZW : RVBUnary<0b011000000001, 0b001, OPC_OP_IMM_32, "ctzw">,
- Sched<[WriteCTZ32, ReadCTZ32]>;
-def CPOPW : RVBUnary<0b011000000010, 0b001, OPC_OP_IMM_32, "cpopw">,
- Sched<[WriteCPOP32, ReadCPOP32]>;
+def CLZW : UnaryW_r<0b011000000000, 0b001, "clzw">,
+ Sched<[WriteCLZ32, ReadCLZ32]>;
+def CTZW : UnaryW_r<0b011000000001, 0b001, "ctzw">,
+ Sched<[WriteCTZ32, ReadCTZ32]>;
+def CPOPW : UnaryW_r<0b011000000010, 0b001, "cpopw">,
+ Sched<[WriteCPOP32, ReadCPOP32]>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
-def SEXT_B : RVBUnary<0b011000000100, 0b001, OPC_OP_IMM, "sext.b">,
+def SEXT_B : Unary_r<0b011000000100, 0b001, "sext.b">,
Sched<[WriteIALU, ReadIALU]>;
-def SEXT_H : RVBUnary<0b011000000101, 0b001, OPC_OP_IMM, "sext.h">,
+def SEXT_H : Unary_r<0b011000000101, 0b001, "sext.h">,
Sched<[WriteIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbb]
@@ -403,28 +397,28 @@ def ZEXT_H_RV64 : RVBUnaryR<0b0000100, 0b100, OPC_OP_32, "zext.h">,
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in {
-def REV8_RV32 : RVBUnary<0b011010011000, 0b101, OPC_OP_IMM, "rev8">,
+def REV8_RV32 : Unary_r<0b011010011000, 0b101, "rev8">,
Sched<[WriteREV8, ReadREV8]>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV32]
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
-def REV8_RV64 : RVBUnary<0b011010111000, 0b101, OPC_OP_IMM, "rev8">,
+def REV8_RV64 : Unary_r<0b011010111000, 0b101, "rev8">,
Sched<[WriteREV8, ReadREV8]>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
let Predicates = [HasStdExtZbb] in {
-def ORC_B : RVBUnary<0b001010000111, 0b101, OPC_OP_IMM, "orc.b">,
+def ORC_B : Unary_r<0b001010000111, 0b101, "orc.b">,
Sched<[WriteORCB, ReadORCB]>;
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbkb] in
-def BREV8 : RVBUnary<0b011010000111, 0b101, OPC_OP_IMM, "brev8">,
+def BREV8 : Unary_r<0b011010000111, 0b101, "brev8">,
Sched<[WriteBREV8, ReadBREV8]>;
let Predicates = [HasStdExtZbkb, IsRV32] in {
-def ZIP_RV32 : RVBUnary<0b000010001111, 0b001, OPC_OP_IMM, "zip">,
+def ZIP_RV32 : Unary_r<0b000010001111, 0b001, "zip">,
Sched<[WriteZIP, ReadZIP]>;
-def UNZIP_RV32 : RVBUnary<0b000010001111, 0b101, OPC_OP_IMM, "unzip">,
+def UNZIP_RV32 : Unary_r<0b000010001111, 0b101, "unzip">,
Sched<[WriteZIP, ReadZIP]>;
} // Predicates = [HasStdExtZbkb, IsRV32]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
index 3ec63b1b6adb33..34f8b006b9c047 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
@@ -52,10 +52,6 @@ def byteselect : RISCVOp<i32>, TImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVKUnary<bits<12> imm12, bits<3> funct3, string opcodestr>
- : RVInstIUnary<imm12, funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
- opcodestr, "$rd, $rs1">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVKByteSelect<bits<5> funct5, string opcodestr>
@@ -88,7 +84,7 @@ let Predicates = [HasStdExtZknd, IsRV64] in {
def AES64DS : ALU_rr<0b0011101, 0b000, "aes64ds">;
def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">;
-def AES64IM : RVKUnary<0b001100000000, 0b001, "aes64im">;
+def AES64IM : Unary_r<0b001100000000, 0b001, "aes64im">;
} // Predicates = [HasStdExtZknd, IsRV64]
let Predicates = [HasStdExtZkndOrZkne, IsRV64] in {
@@ -108,10 +104,10 @@ def AES64ESM : ALU_rr<0b0011011, 0b000, "aes64esm">;
} // Predicates = [HasStdExtZkne, IsRV64]
let Predicates = [HasStdExtZknh], IsSignExtendingOpW = 1 in {
-def SHA256SIG0 : RVKUnary<0b000100000010, 0b001, "sha256sig0">;
-def SHA256SIG1 : RVKUnary<0b000100000011, 0b001, "sha256sig1">;
-def SHA256SUM0 : RVKUnary<0b000100000000, 0b001, "sha256sum0">;
-def SHA256SUM1 : RVKUnary<0b000100000001, 0b001, "sha256sum1">;
+def SHA256SIG0 : Unary_r<0b000100000010, 0b001, "sha256sig0">;
+def SHA256SIG1 : Unary_r<0b000100000011, 0b001, "sha256sig1">;
+def SHA256SUM0 : Unary_r<0b000100000000, 0b001, "sha256sum0">;
+def SHA256SUM1 : Unary_r<0b000100000001, 0b001, "sha256sum1">;
} // Predicates = [HasStdExtZknh]
let Predicates = [HasStdExtZknh, IsRV32] in {
@@ -124,10 +120,10 @@ def SHA512SUM1R : ALU_rr<0b0101001, 0b000, "sha512sum1r">;
} // [HasStdExtZknh, IsRV32]
let Predicates = [HasStdExtZknh, IsRV64] in {
-def SHA512SIG0 : RVKUnary<0b000100000110, 0b001, "sha512sig0">;
-def SHA512SIG1 : RVKUnary<0b000100000111, 0b001, "sha512sig1">;
-def SHA512SUM0 : RVKUnary<0b000100000100, 0b001, "sha512sum0">;
-def SHA512SUM1 : RVKUnary<0b000100000101, 0b001, "sha512sum1">;
+def SHA512SIG0 : Unary_r<0b000100000110, 0b001, "sha512sig0">;
+def SHA512SIG1 : Unary_r<0b000100000111, 0b001, "sha512sig1">;
+def SHA512SUM0 : Unary_r<0b000100000100, 0b001, "sha512sum0">;
+def SHA512SUM1 : Unary_r<0b000100000101, 0b001, "sha512sum1">;
} // Predicates = [HasStdExtZknh, IsRV64]
let Predicates = [HasStdExtZksed], IsSignExtendingOpW = 1 in {
@@ -136,8 +132,8 @@ def SM4KS : RVKByteSelect<0b11010, "sm4ks">;
} // Predicates = [HasStdExtZksed]
let Predicates = [HasStdExtZksh], IsSignExtendingOpW = 1 in {
-def SM3P0 : RVKUnary<0b000100001000, 0b001, "sm3p0">;
-def SM3P1 : RVKUnary<0b000100001001, 0b001, "sm3p1">;
+def SM3P0 : Unary_r<0b000100001000, 0b001, "sm3p0">;
+def SM3P1 : Unary_r<0b000100001001, 0b001, "sm3p1">;
} // Predicates = [HasStdExtZksh]
//===----------------------------------------------------------------------===//
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dtcxzyw
approved these changes
Oct 6, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/4997 Here is the relevant piece of the build log for the reference |
Kyvangka1610
added a commit
to Kyvangka1610/llvm-project
that referenced
this pull request
Oct 7, 2024
* commit 'FETCH_HEAD': [X86] getIntImmCostInst - pull out repeated Imm.getBitWidth() calls. NFC. [X86] Add test coverage for llvm#111323 [Driver] Use empty multilib file in another test (llvm#111352) [clang][OpenMP][test] Use x86_64-linux-gnu triple for test referencing avx512f feature (llvm#111337) [doc] Fix Kaleidoscope tutorial chapter 3 code snippet and full listing discrepancies (llvm#111289) [Flang][OpenMP] Improve entry block argument creation and binding (llvm#110267) [x86] combineMul - handle 0/-1 KnownBits cases before MUL_IMM logic (REAPPLIED) [llvm-dis] Fix non-deterministic disassembly across multiple inputs (llvm#110988) [lldb][test] TestDataFormatterLibcxxOptionalSimulator.py: change order of ifdefs [lldb][test] Add libcxx-simulators test for std::optional (llvm#111133) [x86] combineMul - use computeKnownBits directly to find MUL_IMM constant splat. (REAPPLIED) Reland "[lldb][test] TestDataFormatterLibcxxStringSimulator.py: add new padding layout" (llvm#111123) Revert "[x86] combineMul - use computeKnownBits directly to find MUL_IMM constant splat." update_test_checks: fix a simple regression (llvm#111347) [LegalizeVectorTypes] Always widen fabs (llvm#111298) [lsan] Make ReportUnsuspendedThreads return bool also for Fuchsia [mlir][vector] Add more tests for ConvertVectorToLLVM (6/n) (llvm#111121) [bazel] port 9144fed [SystemZ] Remove inlining threshold multiplier. (llvm#106058) [LegalizeVectorTypes] When widening don't check for libcalls if promoted (llvm#111297) [clang][Driver] Improve multilib custom error reporting (llvm#110804) [clang][Driver] Rename "FatalError" key to "Error" in multilib.yaml (llvm#110804) [LLVM][Maintainers] Update release managers (llvm#111164) [Clang][Driver] Add option to provide path for multilib's YAML config file (llvm#109640) [LoopVectorize] Remove redundant code in emitSCEVChecks (llvm#111132) [AMDGPU] Only emit SCOPE_SYS global_wb (llvm#110636) [ELF] Change Ctx::target to unique_ptr (llvm#111260) [ELF] Pass Ctx & to some free functions [RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (llvm#111308) [Clang] Remove the special-casing for RequiresExprBodyDecl in BuildResolvedCallExpr() after fd87d76 (llvm#111277) [ELF] Pass Ctx & to InputFile [clang-format] Add AlignFunctionDeclarations to AlignConsecutiveDeclarations (llvm#108241) [AMDGPU] Support preloading hidden kernel arguments (llvm#98861) [ELF] Move static nextGroupId isInGroup to LinkerDriver [clangd] Add ArgumentLists config option under Completion (llvm#111322) [ELF] Pass Ctx & to SyntheticSections [ELF] Pass Ctx & to Symbols [ELF] Pass Ctx & to Symbols [ELF] getRelocTargetVA: pass Ctx and Relocation. NFC [clang-tidy] Avoid capturing a local variable in a static lambda in UseRangesCheck (llvm#111282) [VPlan] Use pointer to member 0 as VPInterleaveRecipe's pointer arg. (llvm#106431) [clangd] Simplify ternary expressions with std::optional::value_or (NFC) (llvm#111309) [libc++][format][2/3] Optimizes c-string arguments. (llvm#101805) [RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (llvm#111279) [ELF] Pass Ctx & to InputFiles [libc] GPU RPC interface: add return value to `rpc_host_call` (llvm#111288) Signed-off-by: kyvangka1610 <[email protected]>
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Create Unary_r and UnaryW_r that use OP_IMM and OP_IMM_32.