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[RISCV] Unify RVBShift_ri and RVBShiftW_ri with Shift_ri and ShiftW_ri. NFC #111263

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Merged
merged 1 commit into from
Oct 6, 2024
Merged

[RISCV] Unify RVBShift_ri and RVBShiftW_ri with Shift_ri and ShiftW_ri. NFC #111263

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24 changes: 14 additions & 10 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -558,8 +558,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class Shift_ri<bits<5> imm11_7, bits<3> funct3, string opcodestr>
: RVInstIShift<imm11_7, funct3, OPC_OP_IMM, (outs GPR:$rd),
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
"$rd, $rs1, $shamt">,
Sched<[WriteShiftImm, ReadShiftImm]>;
"$rd, $rs1, $shamt">;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
Expand All @@ -586,8 +585,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class ShiftW_ri<bits<7> imm11_5, bits<3> funct3, string opcodestr>
: RVInstIShiftW<imm11_5, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
(ins GPR:$rs1, uimm5:$shamt), opcodestr,
"$rd, $rs1, $shamt">,
Sched<[WriteShiftImm32, ReadShiftImm32]>;
"$rd, $rs1, $shamt">;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
Expand Down Expand Up @@ -666,9 +664,12 @@ def ORI : ALU_ri<0b110, "ori">;

def ANDI : ALU_ri<0b111, "andi">;

def SLLI : Shift_ri<0b00000, 0b001, "slli">;
def SRLI : Shift_ri<0b00000, 0b101, "srli">;
def SRAI : Shift_ri<0b01000, 0b101, "srai">;
def SLLI : Shift_ri<0b00000, 0b001, "slli">,
Sched<[WriteShiftImm, ReadShiftImm]>;
def SRLI : Shift_ri<0b00000, 0b101, "srli">,
Sched<[WriteShiftImm, ReadShiftImm]>;
def SRAI : Shift_ri<0b01000, 0b101, "srai">,
Sched<[WriteShiftImm, ReadShiftImm]>;

def ADD : ALU_rr<0b0000000, 0b000, "add", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
Expand Down Expand Up @@ -764,9 +765,12 @@ def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),
"addiw", "$rd, $rs1, $imm12">,
Sched<[WriteIALU32, ReadIALU32]>;

def SLLIW : ShiftW_ri<0b0000000, 0b001, "slliw">;
def SRLIW : ShiftW_ri<0b0000000, 0b101, "srliw">;
def SRAIW : ShiftW_ri<0b0100000, 0b101, "sraiw">;
def SLLIW : ShiftW_ri<0b0000000, 0b001, "slliw">,
Sched<[WriteShiftImm32, ReadShiftImm32]>;
def SRLIW : ShiftW_ri<0b0000000, 0b101, "srliw">,
Sched<[WriteShiftImm32, ReadShiftImm32]>;
def SRAIW : ShiftW_ri<0b0100000, 0b101, "sraiw">,
Sched<[WriteShiftImm32, ReadShiftImm32]>;

def ADDW : ALUW_rr<0b0000000, 0b000, "addw", Commutable=1>,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
Expand Down
19 changes: 6 additions & 13 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
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Original file line number Diff line number Diff line change
Expand Up @@ -237,13 +237,6 @@ class RVBShift_ri<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
"$rd, $rs1, $shamt">;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBShiftW_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
string opcodestr>
: RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
(ins GPR:$rs1, uimm5:$shamt), opcodestr,
"$rd, $rs1, $shamt">;

//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -285,7 +278,7 @@ def ROL : ALU_rr<0b0110000, 0b001, "rol">,
def ROR : ALU_rr<0b0110000, 0b101, "ror">,
Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;

def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
def RORI : Shift_ri<0b01100, 0b101, "rori">,
Sched<[WriteRotateImm, ReadRotateImm]>;
} // Predicates = [HasStdExtZbbOrZbkb]

Expand All @@ -295,7 +288,7 @@ def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;

def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
def RORIW : ShiftW_ri<0b0110000, 0b101, "roriw">,
Sched<[WriteRotateImm32, ReadRotateImm32]>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]

Expand All @@ -310,14 +303,14 @@ let IsSignExtendingOpW = 1 in
def BEXT : ALU_rr<0b0100100, 0b101, "bext">,
Sched<[WriteBEXT, ReadSingleBit, ReadSingleBit]>;

def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">,
def BCLRI : Shift_ri<0b01001, 0b001, "bclri">,
Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">,
def BSETI : Shift_ri<0b00101, 0b001, "bseti">,
Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">,
def BINVI : Shift_ri<0b01101, 0b001, "binvi">,
Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
let IsSignExtendingOpW = 1 in
def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">,
def BEXTI : Shift_ri<0b01001, 0b101, "bexti">,
Sched<[WriteBEXTI, ReadSingleBitImm]>;
} // Predicates = [HasStdExtZbs]

Expand Down
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