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[RISCV][ISel] Allow emitting addiw with u32simm12 rhs #111116

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Merged
merged 2 commits into from
Oct 5, 2024
Merged

[RISCV][ISel] Allow emitting addiw with u32simm12 rhs #111116

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826b1cb
[RISCV][ISel] Add pre-commit tests. NFC.
dtcxzyw Oct 4, 2024
949744e
[RISCV][ISel] Allow emit addiw with u32simm12 rhs
dtcxzyw Oct 4, 2024
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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1896,6 +1896,7 @@ def : PatGprGpr<shiftopw<riscv_sraw>, SRAW>;
// Select W instructions if only the lower 32 bits of the result are used.
def : PatGprGpr<binop_allwusers<add>, ADDW>;
def : PatGprSimm12<binop_allwusers<add>, ADDIW>;
def : PatGprImm<binop_allwusers<add>, ADDIW, u32simm12>;
def : PatGprGpr<binop_allwusers<sub>, SUBW>;
def : PatGprImm<binop_allwusers<shl>, SLLIW, uimm5>;

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22 changes: 22 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64zba.ll
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Expand Up @@ -3217,3 +3217,25 @@ entry:
%z = and i64 %y, -8192
ret i64 %z
}

define i64 @add_u32simm32_zextw(i64 %x) nounwind {
; RV64I-LABEL: add_u32simm32_zextw:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: add_u32simm32_zextw:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: addi a0, a0, -2
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret
entry:
%add = add i64 %x, 4294967294
%and = and i64 %add, 4294967295
ret i64 %and
}
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