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[AArch64] Make apple-m4 armv8.7-a again (from armv9.2-a). #106312

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Merged
merged 2 commits into from
Aug 29, 2024
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[AArch64] Make apple-m4 armv8.7-a again (from armv9.2-a). #106312

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c9b2837
[AArch64] Add incorrect target(cpu=apple-m4) fn attr test. NFC.
ahmedbougacha Aug 27, 2024
1a16e34
[AArch64] Make apple-m4 armv8.7-a again (from armv9.2-a).
ahmedbougacha Aug 27, 2024
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9 changes: 9 additions & 0 deletions clang/test/CodeGen/aarch64-targetattr.c
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Expand Up @@ -191,6 +191,14 @@ __attribute__((target("no-v9.3a")))
//
void minusarch() {}

__attribute__((target("cpu=apple-m4")))
// CHECK-LABEL: define {{[^@]+}}@applem4
// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret void
//
void applem4() {}

//.
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
Expand All @@ -210,6 +218,7 @@ void minusarch() {}
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
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7 changes: 6 additions & 1 deletion llvm/lib/Target/AArch64/AArch64Processors.td
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Expand Up @@ -895,7 +895,12 @@ def ProcessorFeatures {
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleM4 = [HasV9_2aOps, FeatureSHA2, FeatureFPARMv8,
// Technically apple-m4 is v9.2a, but we can't use that here.
// Historically, llvm defined v9.0a as requiring SVE, but it's optional
// according to the Arm ARM, and not supported by the core. We decoupled the
// two in the clang driver and in the backend subtarget features, but it's
// still an issue in the clang frontend. v8.7a is the next closest choice.
list<SubtargetFeature> AppleM4 = [HasV8_7aOps, FeatureSHA2, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureAES, FeatureBF16,
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2 changes: 1 addition & 1 deletion llvm/unittests/TargetParser/TargetParserTest.cpp
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Expand Up @@ -1122,7 +1122,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUTestParams("apple-a16", "armv8.6-a"),
AArch64CPUTestParams("apple-m3", "armv8.6-a"),
AArch64CPUTestParams("apple-a17", "armv8.6-a"),
AArch64CPUTestParams("apple-m4", "armv9.2-a"),
AArch64CPUTestParams("apple-m4", "armv8.7-a"),
AArch64CPUTestParams("exynos-m3", "armv8-a"),
AArch64CPUTestParams("exynos-m4", "armv8.2-a"),
AArch64CPUTestParams("exynos-m5", "armv8.2-a"),
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