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[PowerPC] Fix mask for __st[d/w/h/b]cx builtins #104453

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Merged
merged 2 commits into from
Aug 22, 2024
Merged

[PowerPC] Fix mask for __st[d/w/h/b]cx builtins #104453

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2b1cd10
[PowerPC] Fix mask for __st[d/w/h/b]cx builtins
Aug 15, 2024
519cce9
Address review comments
Aug 19, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2016,9 +2016,9 @@ def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
} // IsISA3_0

def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
(STDCX g8rc:$A, ForceXForm:$dst)>;
(RLWINM (STDCX g8rc:$A, ForceXForm:$dst), 31, 31, 31)>;
def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8),
(STDCX g8rc:$A, ForceXForm:$dst)>;
(RLWINM (STDCX g8rc:$A, ForceXForm:$dst), 31, 31, 31)>;

def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
(MFSPR8 $SPR)>;
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12 changes: 6 additions & 6 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
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Expand Up @@ -5288,13 +5288,13 @@ def : Pat<(i64 (bitreverse i64:$A)),
(OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;

def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
(STWCX gprc:$A, ForceXForm:$dst)>;
(RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;
def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4),
(STWCX gprc:$A, ForceXForm:$dst)>;
(RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;
def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
(STBCX gprc:$A, ForceXForm:$dst)>;
(RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;
def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1),
(STBCX gprc:$A, ForceXForm:$dst)>;
(RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;

def : Pat<(int_ppc_fcfid f64:$A),
(XSCVSXDDP $A)>;
Expand Down Expand Up @@ -5324,9 +5324,9 @@ def : Pat<(int_ppc_mtmsr gprc:$RS),

let Predicates = [IsISA2_07] in {
def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A),
(STHCX gprc:$A, ForceXForm:$dst)>;
(RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;
def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2),
(STHCX gprc:$A, ForceXForm:$dst)>;
(RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>;
}
def : Pat<(int_ppc_dcbtstt ForceXForm:$dst),
(DCBTST 16, ForceXForm:$dst)>;
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
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Expand Up @@ -26,7 +26,7 @@ define dso_local i64 @test_stdcx(ptr %a, i64 %b) {
; CHECK-NEXT: stdcx. 4, 0, 3
; CHECK-NEXT: mfocrf 3, 128
; CHECK-NEXT: srwi 3, 3, 28
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.stdcx(ptr %a, i64 %b)
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9 changes: 6 additions & 3 deletions llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
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Expand Up @@ -36,14 +36,15 @@ define dso_local signext i32 @test_stwcx(ptr %a, i32 signext %b) {
; CHECK-64-NEXT: stwcx. 4, 0, 3
; CHECK-64-NEXT: mfocrf 3, 128
; CHECK-64-NEXT: srwi 3, 3, 28
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-64-NEXT: blr
;
; CHECK-32-LABEL: test_stwcx:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: stwcx. 4, 0, 3
; CHECK-32-NEXT: mfocrf 3, 128
; CHECK-32-NEXT: srwi 3, 3, 28
; CHECK-32-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-32-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.stwcx(ptr %a, i32 %b)
Expand All @@ -57,14 +58,15 @@ define dso_local signext i32 @test_sthcx(ptr %a, i16 signext %val) {
; CHECK-64-NEXT: sthcx. 4, 0, 3
; CHECK-64-NEXT: mfocrf 3, 128
; CHECK-64-NEXT: srwi 3, 3, 28
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-64-NEXT: blr
;
; CHECK-32-LABEL: test_sthcx:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: sthcx. 4, 0, 3
; CHECK-32-NEXT: mfocrf 3, 128
; CHECK-32-NEXT: srwi 3, 3, 28
; CHECK-32-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-32-NEXT: blr
entry:
%0 = sext i16 %val to i32
Expand All @@ -79,14 +81,15 @@ define signext i32 @test_stbcx(ptr %addr, i8 signext %val) {
; CHECK-64-NEXT: stbcx. 4, 0, 3
; CHECK-64-NEXT: mfocrf 3, 128
; CHECK-64-NEXT: srwi 3, 3, 28
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-64-NEXT: blr
;
; CHECK-32-LABEL: test_stbcx:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: stbcx. 4, 0, 3
; CHECK-32-NEXT: mfocrf 3, 128
; CHECK-32-NEXT: srwi 3, 3, 28
; CHECK-32-NEXT: rlwinm 3, 3, 31, 31, 31
; CHECK-32-NEXT: blr
entry:
%conv = sext i8 %val to i32
Expand Down
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